adc_seg8_display.tan.summary

VHDLADC数码管动态扫描.rar

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.000 ns
From           : EOC
To             : ADCINT:inst3|current_state.state_bit_0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 53.000 ns
From           : ADCINT:inst3|REGL[2]
To             : BCD_DATA[3]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.000 ns
From           : ADC_D[7]
To             : ADCINT:inst3|REGL[7]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : SEG8_DISPLAY:inst|CNT[1]
To             : SEG8_DISPLAY:inst|CNT[1]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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