adc_seg8_display.tan.rpt

VHDLADC数码管动态扫描.rar

; N/A   ; None         ; 17.000 ns  ; SEG8_DISPLAY:inst|CNT[1]               ; COM[3]      ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; ADCINT:inst3|current_state.state_bit_0 ; START       ; CLK        ;
; N/A   ; None         ; 17.000 ns  ; ADCINT:inst3|current_state.state_bit_1 ; START       ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; ADCINT:inst3|current_state.state_bit_2 ; LOCK0       ; CLK        ;
+-------+--------------+------------+----------------------------------------+-------------+------------+


+--------------------------------------------------------------------------------------------------------+
; th                                                                                                     ;
+---------------+-------------+-----------+----------+----------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To                                     ; To Clock ;
+---------------+-------------+-----------+----------+----------------------------------------+----------+
; N/A           ; None        ; 6.000 ns  ; ADC_D[0] ; ADCINT:inst3|REGL[0]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[1] ; ADCINT:inst3|REGL[1]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[2] ; ADCINT:inst3|REGL[2]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[3] ; ADCINT:inst3|REGL[3]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[4] ; ADCINT:inst3|REGL[4]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[5] ; ADCINT:inst3|REGL[5]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[6] ; ADCINT:inst3|REGL[6]                   ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ADC_D[7] ; ADCINT:inst3|REGL[7]                   ; CLK      ;
; N/A           ; None        ; -3.000 ns ; EOC      ; ADCINT:inst3|current_state.state_bit_0 ; CLK      ;
+---------------+-------------+-----------+----------+----------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Apr 14 19:34:40 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADC_SEG8_DISPLAY -c ADC_SEG8_DISPLAY
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "ADCINT:inst3|current_state.state_bit_2" as buffer
Info: Clock "CLK" has Internal fmax of 76.92 MHz between source register "SEG8_DISPLAY:inst|CNT[0]" and destination register "SEG8_DISPLAY:inst|CNT[0]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst|CNT[0]'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst|CNT[0]'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst|CNT[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 101; REG Node = 'SEG8_DISPLAY:inst|CNT[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "ADCINT:inst3|current_state.state_bit_0" (data pin = "EOC", clock pin = "CLK") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_59; Fanout = 1; PIN Node = 'EOC'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC64; Fanout = 7; REG Node = 'ADCINT:inst3|current_state.state_bit_0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC64; Fanout = 7; REG Node = 'ADCINT:inst3|current_state.state_bit_0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "BCD_DATA[3]" through register "ADCINT:inst3|REGL[7]" is 53.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC29; Fanout = 11; REG Node = 'ADCINT:inst3|current_state.state_bit_2'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC48; Fanout = 96; REG Node = 'ADCINT:inst3|REGL[7]'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 40.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC48; Fanout = 96; REG Node = 'ADCINT:inst3|REGL[7]'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP25; Fanout = 1; COMB Node = 'TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~122'
        Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC18; Fanout = 1; COMB Node = 'TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~140'
        Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 18.000 ns; Loc. = LC19; Fanout = 25; COMB Node = 'TWO_TO_BCD:inst12|DIVI:inst1|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7|add_sub_cella[2]~129'
        Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 28.000 ns; Loc. = SEXP78; Fanout = 2; COMB Node = 'SEG8_DISPLAY:inst|Mux26~246'
        Info: 6: + IC(0.000 ns) + CELL(6.000 ns) = 34.000 ns; Loc. = LC66; Fanout = 1; COMB Node = 'SEG8_DISPLAY:inst|Mux26~272'
        Info: 7: + IC(0.000 ns) + CELL(2.000 ns) = 36.000 ns; Loc. = LC67; Fanout = 1; COMB Node = 'SEG8_DISPLAY:inst|Mux26~263'
        Info: 8: + IC(0.000 ns) + CELL(4.000 ns) = 40.000 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'BCD_DATA[3]'
        Info: Total cell delay = 36.000 ns ( 90.00 % )
        Info: Total interconnect delay = 4.000 ns ( 10.00 % )
Info: th for register "ADCINT:inst3|REGL[0]" (data pin = "ADC_D[0]", clock pin = "CLK") is 6.000 ns
    Info: + Longest clock path from clock "CLK" to destination register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_89; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC29; Fanout = 11; REG Node = 'ADCINT:inst3|current_state.state_bit_2'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC61; Fanout = 34; REG Node = 'ADCINT:inst3|REGL[0]'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_73; Fanout = 1; PIN Node = 'ADC_D[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC61; Fanout = 34; REG Node = 'ADCINT:inst3|REGL[0]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 104 megabytes of memory during processing
    Info: Processing ended: Wed Apr 14 19:34:41 2010
    Info: Elapsed time: 00:00:01