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📄 adc_seg8_display.vho

📁 VHDLADC数码管动态扫描.rar
💻 VHO
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SIGNAL \inst|Mux25~130_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux7~137_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~136_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~257_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux26~263_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~393_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1466_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1472_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1478_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1484_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~136_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~140_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~651_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~653_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1490_pena_bus\ : std_logic_vector(51 DOWNTO 0);
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