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📄 adc_seg8_display.vho

📁 VHDLADC数码管动态扫描.rar
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SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[49]~1446_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[50]~1453_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_7|add_sub_cella[2]~129_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_6|add_sub_cella[4]~650_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|StageOut[51]~1465_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~36_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~100_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux27~92_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~311_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux29~233_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~104_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~110_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux24~115_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux25~130_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
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