adc_seg8_display.vho

VHDLADC数码管动态扫描.rar

SIGNAL \inst3|current_state.state_bit_0_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~26_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_2_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[7]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[6]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[5]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[4]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[3]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[2]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|OE~6_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[1]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|REGL[0]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux22~20_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_5|add_sub_cella[4]~392_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst12|inst1|lpm_divide_component|auto_generated|divider|divider|add_sub_4|_~68_pxor_bus\ : std_logic_vector(51 DOWNTO 0);