adc_seg8_display.vho

VHDLADC数码管动态扫描.rar

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

-- DATE "04/14/2010 19:34:43"

-- 
-- Device: Altera EPM7128SQC100-15 Package PQFP100
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	ADC_SEG8_DISPLAY IS
    PORT (
	LOCK0 : OUT std_logic;
	CLK : IN std_logic;
	EOC : IN std_logic;
	ADC_D : IN std_logic_vector(7 DOWNTO 0);
	ALE : OUT std_logic;
	START : OUT std_logic;
	OE : OUT std_logic;
	ADDA : OUT std_logic;
	BCD_DATA : OUT std_logic_vector(7 DOWNTO 0);
	COM : OUT std_logic_vector(3 DOWNTO 0)
	);
END ADC_SEG8_DISPLAY;

ARCHITECTURE structure OF ADC_SEG8_DISPLAY IS
SIGNAL GNDs : std_logic_vector(2048 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(2048 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL ww_LOCK0 : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_EOC : std_logic;
SIGNAL ww_ADC_D : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_ALE : std_logic;
SIGNAL ww_START : std_logic;
SIGNAL ww_OE : std_logic;
SIGNAL ww_ADDA : std_logic;
SIGNAL ww_BCD_DATA : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_COM : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|CNT[0]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[0]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.st1~24_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_1_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|CNT[1]_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux23~299_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~21_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux30~36_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst|Mux28~25_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \inst3|current_state.state_bit_0_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);