adc_seg8_display.map.rpt

VHDLADC数码管动态扫描.rar

; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                    ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                  ;
+------------------------+----------------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Apr 14 19:29:23 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADC_SEG8_DISPLAY -c ADC_SEG8_DISPLAY
Info: Found 1 design units, including 1 entities, in source file ../TWO_TO_BCD/Block2.bdf
    Info: Found entity 1: Block2
Info: Found 2 design units, including 1 entities, in source file ../TWO_TO_BCD/DIVI.vhd
    Info: Found design unit 1: divi-SYN
    Info: Found entity 1: DIVI
Info: Found 1 design units, including 1 entities, in source file ../TWO_TO_BCD/TWO_TO_BCD.bdf
    Info: Found entity 1: TWO_TO_BCD
Info: Found 2 design units, including 1 entities, in source file ../SEG8_DISPLAY/SEG8_DISPLAY.vhd
    Info: Found design unit 1: SEG8_DISPLAY-BEHAV
    Info: Found entity 1: SEG8_DISPLAY
Info: Found 1 design units, including 1 entities, in source file ../ADCINT/Block1.bdf
    Info: Found entity 1: Block1
Info: Found 2 design units, including 1 entities, in source file ../ADCINT/ADCINT.vhd
    Info: Found design unit 1: ADCINT-behav
    Info: Found entity 1: ADCINT
Info: Found 1 design units, including 1 entities, in source file ADC_SEG8_DISPLAY.bdf
    Info: Found entity 1: ADC_SEG8_DISPLAY
Info: Elaborating entity "ADC_SEG8_DISPLAY" for the top level hierarchy
Info: Elaborating entity "ADCINT" for hierarchy "ADCINT:inst3"
Info: Elaborating entity "SEG8_DISPLAY" for hierarchy "SEG8_DISPLAY:inst"
Warning (10492): VHDL Process Statement warning at SEG8_DISPLAY.vhd(34): signal "DIS_HDD_DATA" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SEG8_DISPLAY.vhd(48): signal "DIS_TEN_DATA" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SEG8_DISPLAY.vhd(62): signal "DIS_IND_DATA" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SEG8_DISPLAY.vhd(78): signal "SEG8_BCD_DATA_BUF" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "TWO_TO_BCD" for hierarchy "TWO_TO_BCD:inst12"
Info: Elaborating entity "DIVI" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborating entity "lpm_divide" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component"
Info: Elaborated megafunction instantiation "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_pgp.tdf
    Info: Found entity 1: lpm_divide_pgp
Info: Elaborating entity "lpm_divide_pgp" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_jkh.tdf
    Info: Found entity 1: sign_div_unsign_jkh
Info: Elaborating entity "sign_div_unsign_jkh" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider"
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_5le.tdf
    Info: Found entity 1: alt_u_div_5le
Info: Elaborating entity "alt_u_div_5le" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_m9c.tdf
    Info: Found entity 1: add_sub_m9c
Info: Elaborating entity "add_sub_m9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_m9c:add_sub_0"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_n9c.tdf
    Info: Found entity 1: add_sub_n9c
Info: Elaborating entity "add_sub_n9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_n9c:add_sub_1"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_o9c.tdf
    Info: Found entity 1: add_sub_o9c
Info: Elaborating entity "add_sub_o9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_o9c:add_sub_2"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_p9c.tdf
    Info: Found entity 1: add_sub_p9c
Info: Elaborating entity "add_sub_p9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_p9c:add_sub_3"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_q9c.tdf
    Info: Found entity 1: add_sub_q9c
Info: Elaborating entity "add_sub_q9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_q9c:add_sub_4"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_r9c.tdf
    Info: Found entity 1: add_sub_r9c
Info: Elaborating entity "add_sub_r9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_r9c:add_sub_5"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_s9c.tdf
    Info: Found entity 1: add_sub_s9c
Info: Elaborating entity "add_sub_s9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_s9c:add_sub_6"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_t9c.tdf
    Info: Found entity 1: add_sub_t9c
Info: Elaborating entity "add_sub_t9c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|alt_u_div_5le:divider|add_sub_t9c:add_sub_7"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_s5c.tdf
    Info: Found entity 1: add_sub_s5c
Info: Elaborating entity "add_sub_s5c" for hierarchy "TWO_TO_BCD:inst12|DIVI:inst|lpm_divide:lpm_divide_component|lpm_divide_pgp:auto_generated|sign_div_unsign_jkh:divider|add_sub_s5c:adder"
Info: Ignored 45 buffer(s)
    Info: Ignored 45 CARRY_SUM buffer(s)
Info: State machine "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state"
Info: Encoding result for state machine "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "ADCINT:inst3|current_state.state_bit_2"
        Info: Encoded state bit "ADCINT:inst3|current_state.state_bit_1"
        Info: Encoded state bit "ADCINT:inst3|current_state.state_bit_0"
    Info: State "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state.st0" uses code string "000"
    Info: State "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state.st1" uses code string "001"
    Info: State "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state.st2" uses code string "010"
    Info: State "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state.st3" uses code string "011"
    Info: State "|ADC_SEG8_DISPLAY|ADCINT:inst3|current_state.st4" uses code string "100"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ADDA" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 123 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 17 output pins
    Info: Implemented 70 macrocells
    Info: Implemented 26 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Allocated 152 megabytes of memory during processing
    Info: Processing ended: Wed Apr 14 19:34:34 2010
    Info: Elapsed time: 00:05:11