spi_master_timesim.vhd

SPI.zip

  signal addr_data_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal FOOBAR2_ctinst_0 : STD_LOGIC; 
  signal FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal N_PZ_721_MC_Q : STD_LOGIC; 
  signal N_PZ_721_MC_D : STD_LOGIC; 
  signal N_PZ_721_MC_D1 : STD_LOGIC; 
  signal N_PZ_721_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_721_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_721_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_721_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_721_MC_D2 : STD_LOGIC; 
  signal uc_intrface_ssel_en_MC_Q : STD_LOGIC; 
  signal uc_intrface_ssel_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_ssel_en_MC_D : STD_LOGIC; 
  signal uc_intrface_ssel_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_intrface_ssel_en_MC_D1 : STD_LOGIC; 
  signal uc_intrface_ssel_en_MC_D2 : STD_LOGIC; 
  signal uc_intrface_rcv_en_MC_Q : STD_LOGIC; 
  signal uc_intrface_rcv_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_rcv_en_MC_D : STD_LOGIC; 
  signal uc_intrface_rcv_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_intrface_rcv_en_MC_D1 : STD_LOGIC; 
  signal uc_intrface_rcv_en_MC_D2 : STD_LOGIC; 
  signal uc_intrface_xmit_en_MC_Q : STD_LOGIC; 
  signal uc_intrface_xmit_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_xmit_en_MC_D : STD_LOGIC; 
  signal uc_intrface_xmit_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_intrface_xmit_en_MC_D1 : STD_LOGIC; 
  signal uc_intrface_xmit_en_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_Q : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_D : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_D1 : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_D2 : STD_LOGIC; 
  signal uc_intrface_spissr_0_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_Q : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D1 : STD_LOGIC; 
  signal N_PZ_666 : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_pos : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_miso_neg : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_n00012 : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_intrface_spirr_0_MC_D2 : STD_LOGIC; 
  signal N_PZ_666_MC_Q : STD_LOGIC; 
  signal N_PZ_666_MC_D : STD_LOGIC; 
  signal N_PZ_666_MC_D1 : STD_LOGIC; 
  signal sck_MC_UIM : STD_LOGIC; 
  signal N_PZ_654 : STD_LOGIC; 
  signal N_PZ_666_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_cpol : STD_LOGIC; 
  signal N_PZ_666_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_666_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_666_MC_D2 : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_Q : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_D : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_D1 : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_D2 : STD_LOGIC; 
  signal uc_intrface_rcv_cpol_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1_MC_Q : STD_LOGIC; 
  signal FOOBAR7_ctinst_1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1_MC_D : STD_LOGIC; 
  signal FOOBAR7_ctinst_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_d1_MC_D2 : STD_LOGIC; 
  signal sck_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sck_MC_Q : STD_LOGIC; 
  signal FOOBAR6_ctinst_0 : STD_LOGIC; 
  signal sck_MC_R_OR_PRLD : STD_LOGIC; 
  signal sck_MC_D : STD_LOGIC; 
  signal FOOBAR6_ctinst_1 : STD_LOGIC; 
  signal FOOBAR6_ctinst_4 : STD_LOGIC; 
  signal sck_II_UIM : STD_LOGIC; 
  signal FOOBAR6_ctinst_5 : STD_LOGIC; 
  signal N_PZ_654_MC_Q : STD_LOGIC; 
  signal N_PZ_654_MC_D : STD_LOGIC; 
  signal N_PZ_654_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1 : STD_LOGIC; 
  signal N_PZ_654_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_654_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_654_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_Q : STD_LOGIC; 
  signal FOOBAR1_ctinst_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft3_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_1 : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal spi_intrface_sck_1 : STD_LOGIC; 
  signal FOOBAR1_ctinst_7 : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_intrface_cpha : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2_PT_4 : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2_PT_5 : STD_LOGIC; 
  signal spi_intrface_sck_1_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft4_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D1 : STD_LOGIC; 
  signal N_PZ_662 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_724 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft2_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_662_MC_Q : STD_LOGIC; 
  signal N_PZ_662_MC_D : STD_LOGIC; 
  signal N_PZ_662_MC_D1 : STD_LOGIC; 
  signal N_PZ_662_MC_D2_PT_0 : STD_LOGIC; 
  signal xmit_empty_MC_UIM : STD_LOGIC; 
  signal uc_intrface_start : STD_LOGIC; 
  signal N_PZ_662_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_662_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_Q : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_4 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_5 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_6 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n0076 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2_PT_7 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D2 : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_spi_state_fft1_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D2_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D2_PT_1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D2_PT_2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D2_PT_3 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_MC_D2 : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_Q : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_D : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_D1 : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_D2 : STD_LOGIC; 
  signal uc_intrface_clkdiv_1_MC_D_TFF : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_Q : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_D : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_D1 : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_D2 : STD_LOGIC; 
  signal uc_intrface_clkdiv_0_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_D2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_n0020_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_D2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_3_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_D2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_2_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_D2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_cnt_1_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_divdr_qout_0_MC_Q : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_divdr_qout_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_divdr_qout_0_MC_D : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_divdr_qout_0_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_divdr_qout_0_MC_D2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_clk_divdr_qout_0_MC_D_TFF : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1_MC_Q : STD_LOGIC; 
  signal FOOBAR8_ctinst_1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1_MC_R_OR_PRLD : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1_MC_D : STD_LOGIC; 
  signal FOOBAR8_ctinst_0 : STD_LOGIC; 
  signal FOOBAR8_ctinst_2 : STD_LOGIC; 
  signal FOOBAR8_ctinst_4 : STD_LOGIC; 
  signal FOOBAR8_ctinst_5 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_n00012_MC_Q : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_n00012_MC_D : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_n00012_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_n00012_MC_D1 : STD_LOGIC; 
  signal spi_intrface_rcv_shift_reg_n00012_MC_D2 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1_MC_D1_PT_0 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1_MC_D1 : STD_LOGIC; 
  signal spi_intrface_sck_gen_sck_int_d1_MC_D2 : STD_LOGIC; 
  signal xmit_empty_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal xmit_empty_MC_Q : STD_LOGIC; 
  signal FOOBAR10_ctinst_0 : STD_LOGIC; 
  signal xmit_empty_MC_R_OR_PRLD : STD_LOGIC; 
  signal xmit_empty_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_7_tsimcreated_inv_Q : STD_LOGIC; 
  signal FOOBAR10_ctinst_4 : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset : STD_LOGIC; 
  signal spi_intrface_spi_ctrl_sm_n00822 : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_Q : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_D : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_D1 : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_intrface_xmit_empty_reset_MC_D2_PT_1 : STD_LOGIC;