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📄 lcd1602.tan.rpt

📁 LCD1602.rar
💻 RPT
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; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                           ; To                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[2]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[3]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[0]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[1]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[4]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[5]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[6]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 87.28 MHz ( period = 11.457 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Address[7]          ; CLK        ; CLK      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[2]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[3]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[0]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[1]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[4]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[5]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[6]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 88.65 MHz ( period = 11.280 ns )                    ; LCD_CLK:circuit1|Count_Lcd[9]  ; Address[7]          ; CLK        ; CLK      ; None                        ; None                      ; 10.571 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[2]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[3]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[0]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[1]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[4]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[5]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[6]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.01 MHz ( period = 11.110 ns )                    ; LCD_CLK:circuit1|Count_Lcd[11] ; Address[7]          ; CLK        ; CLK      ; None                        ; None                      ; 10.401 ns               ;
; N/A                                     ; 90.63 MHz ( period = 11.034 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; DB[7]~reg0          ; CLK        ; CLK      ; None                        ; None                      ; 10.325 ns               ;
; N/A                                     ; 91.11 MHz ( period = 10.976 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; DB[6]~reg0          ; CLK        ; CLK      ; None                        ; None                      ; 10.267 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[115] ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[105] ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[107] ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[97]  ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[99]  ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[100] ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[89]  ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[91]  ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[81]  ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.20 MHz ( period = 10.965 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[83]  ; CLK        ; CLK      ; None                        ; None                      ; 10.256 ns               ;
; N/A                                     ; 91.48 MHz ( period = 10.931 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[104] ; CLK        ; CLK      ; None                        ; None                      ; 10.222 ns               ;
; N/A                                     ; 91.48 MHz ( period = 10.931 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[96]  ; CLK        ; CLK      ; None                        ; None                      ; 10.222 ns               ;
; N/A                                     ; 91.48 MHz ( period = 10.931 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[88]  ; CLK        ; CLK      ; None                        ; None                      ; 10.222 ns               ;
; N/A                                     ; 91.48 MHz ( period = 10.931 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[80]  ; CLK        ; CLK      ; None                        ; None                      ; 10.222 ns               ;
; N/A                                     ; 91.48 MHz ( period = 10.931 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[84]  ; CLK        ; CLK      ; None                        ; None                      ; 10.222 ns               ;
; N/A                                     ; 91.48 MHz ( period = 10.931 ns )                    ; LCD_CLK:circuit1|Count_Lcd[5]  ; Disp_CodeFirst[72]  ; CLK        ; CLK      ; None                        ; None                      ; 10.222 ns               ;

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