mem_interface_top_ram_d_0.txt

DDR_SDRAM_verilog.rar

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_RAM_D_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Contains the distributed RAM which stores IOB output data that 
//              is read from the memory.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_RAM_D_0
  (
   input                        A0,
   input                        A1,
   input                        A2,
   input                        A3,
   input                        DPRA0,
   input                        DPRA1,
   input                        DPRA2,
   input                        DPRA3,
   input                        WCLK,
   input                        WE,
   input [`memory_width-1:0]    D,
   output [`memory_width-1:0]   DPO
   );



   RAM16X1D RAM16X1D0
             ( .D(D[0]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[0]));


RAM16X1D RAM16X1D1
             ( .D(D[1]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[1]));


RAM16X1D RAM16X1D2
             ( .D(D[2]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[2]));


RAM16X1D RAM16X1D3
             ( .D(D[3]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[3]));


RAM16X1D RAM16X1D4
             ( .D(D[4]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[4]));


RAM16X1D RAM16X1D5
             ( .D(D[5]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[5]));


RAM16X1D RAM16X1D6
             ( .D(D[6]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[6]));


RAM16X1D RAM16X1D7
             ( .D(D[7]),
               .WE(WE),
               .WCLK(WCLK),
               .A0(A0),
               .A1(A1),
               .A2(A2),
               .A3(A3),
               .DPRA0(DPRA0),
               .DPRA1(DPRA1),
               .DPRA2(DPRA2),
               .DPRA3(DPRA3),
               .SPO(),
               .DPO(DPO[7]));





endmodule