mem_interface_top_parameters_0.txt

DDR_SDRAM_verilog.rar

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_parameters_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: According to the user inputs the parameters are defined here.
//              These parameters are used for generic memory interface code.
//              Various parameters are address widths, data widths, timing
//              parameters according to the frequency selected by the user
//              and some internal parameters also.
///////////////////////////////////////////////////////////////////////////////

// counter values in the controller in tCK units
`timescale 1ns / 1ps
`define   data_width                               64
`define   data_strobe_width                        8
`define   data_mask_width                          8
`define   clk_width                                4
`define   fifo_16                                  4
`define   ReadEnable                               2
`define   memory_width                             8
`define   DatabitsPerReadClock                     8
`define   DatabitsPerMask                          8
`define   no_of_cs                                 1
`define   data_mask                                1
`define   mask_disable                             0
`define   RESET                                    0
`define   cke_width                                1
`define   registered                               0
`define   col_ap_width                             11
`define   low_frequency                            0
`define   high_frequency                           1
`define   row_address                              12
`define   column_address                           9
`define   bank_address                             2
`define   burst_length                             3'b010
`define   burst_type                               1'b0
`define   cas_latency_value                        3'b011
`define   Operating_mode                           5'b00000
`define   load_mode_register                       12'b000000110010
`define   drive_strengh                            1'b0
`define   dll_enable                               1'b0
`define   ext_load_mode_register                   12'b000000000000
`define   chip_address                             1
`define   reset_active_low                         1'b1
`define   rcd_count_value                          3'b010
`define   ras_count_value                          4'b0110
`define   mrd_count_value                          1'b0
`define   rp_count_value                           3'b010
`define   rfc_count_value                          6'b001100
`define   twr_count_value                          3'b110
`define   twtr_count_value                         3'b100
`define   max_ref_width                            11
`define   max_ref_cnt                        11'b10100110010

`define    Phy_Mode                 1'b1
`define    trtp_count_value         3'b011
`define    rc_count_value         4'b1111   // active to active same bank = tRC-1

// [6:4] cas latency, 010-2, 011-3, 110-2.5
// [2:0] burst length 001-2, 010-4, 011-8