mem_interface_top_tap_logic_0.txt

DDR_SDRAM_verilog.rar

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_tap_logic_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Instantiates the tap_cntrl and the data_tap_inc modules. 
//              Used for calibration of the memory data with the FPGA clock.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_tap_logic_0
  (
   input				CLK,
   input				RESET0,
   input				idelay_ctrl_rdy,
   input				CTRL_DUMMYREAD_START,
   input  [`data_strobe_width-1:0]	dqs_delayed,
   output				SEL_DONE,
   output [`ReadEnable-1:0]		data_idelay_inc,
   output [`ReadEnable-1:0]		data_idelay_ce,
   output [`ReadEnable-1:0]		data_idelay_rst,
   output [`ReadEnable-1:0]		dqs_idelay_inc,
   output [`ReadEnable-1:0]		dqs_idelay_ce,
   output [`ReadEnable-1:0]		dqs_idelay_rst
   );

   reg				data_tap_inc_done;
   reg				tap_sel_done;
   reg				rst_r;

   wire [`ReadEnable-1:0] 	data_tap_select;
   wire [`ReadEnable-1:0] 	dqs_tap_sel_done;
   wire [`ReadEnable-1:0] 	valid_tap_count;


   wire [5:0] data_tap_count0;
wire [5:0] data_tap_count1;


   // For controller to stop dummy reads
   assign SEL_DONE = tap_sel_done;

   always @( posedge CLK )
     rst_r <= RESET0;

   always @ (posedge CLK) begin
      if (rst_r == 1'b1) begin
	 data_tap_inc_done  <= 1'b0;
	 tap_sel_done           <= 1'b0;

      end
      else begin
	 data_tap_inc_done   <= (&data_tap_select[`ReadEnable-1:0]);
	 tap_sel_done           <= (data_tap_inc_done);

      end
   end


   /////////////////////////////////////////////////////////////////////////
   //  tap_ctrl instances for  DDR_DQS strobes
   /////////////////////////////////////////////////////////////////////////

   mem_interface_top_tap_ctrl tap_ctrl_0
            (
              .CLK                    (CLK),
              .RESET                  (RESET0),
              .RDY_STATUS             (idelay_ctrl_rdy),
              .DQS                    (dqs_delayed[3]),
              .CTRL_DUMMYREAD_START   (CTRL_DUMMYREAD_START),
              .DLYINC                 (dqs_idelay_inc[0]),
              .DLYCE                  (dqs_idelay_ce[0]),
              .DLYRST                 (dqs_idelay_rst[0]),
              .SEL_DONE               (dqs_tap_sel_done[0]),
              .VALID_DATA_TAP_COUNT   (valid_tap_count[0]),
              .DATA_TAP_COUNT         (data_tap_count0[5:0])
              );

mem_interface_top_tap_ctrl tap_ctrl_1
            (
              .CLK                    (CLK),
              .RESET                  (RESET0),
              .RDY_STATUS             (idelay_ctrl_rdy),
              .DQS                    (dqs_delayed[7]),
              .CTRL_DUMMYREAD_START   (CTRL_DUMMYREAD_START),
              .DLYINC                 (dqs_idelay_inc[1]),
              .DLYCE                  (dqs_idelay_ce[1]),
              .DLYRST                 (dqs_idelay_rst[1]),
              .SEL_DONE               (dqs_tap_sel_done[1]),
              .VALID_DATA_TAP_COUNT   (valid_tap_count[1]),
              .DATA_TAP_COUNT         (data_tap_count1[5:0])
              );


   /////////////////////////////////////////////////////////////////////////
   //  instances of data_tap_inc for each dqs and associated tap_ctrl
   /////////////////////////////////////////////////////////////////////////

   mem_interface_top_data_tap_inc data_tap_inc_0
            (
                    .CLK                    (CLK),
                    .RESET                  (RESET0),
                    .DATA_DLYINC            (data_idelay_inc[0]),
                    .DATA_DLYCE             (data_idelay_ce[0]),
                    .DATA_DLYRST            (data_idelay_rst[0]),
                    .DATA_TAP_SEL_DONE      (data_tap_select[0]),
                    .DQS_sel_done           (dqs_tap_sel_done[0]),
                    .VALID_DATA_TAP_COUNT   (valid_tap_count[0]),
                    .DATA_TAP_COUNT         (data_tap_count0[5:0])
                                );


mem_interface_top_data_tap_inc data_tap_inc_1
            (
                    .CLK                    (CLK),
                    .RESET                  (RESET0),
                    .DATA_DLYINC            (data_idelay_inc[1]),
                    .DATA_DLYCE             (data_idelay_ce[1]),
                    .DATA_DLYRST            (data_idelay_rst[1]),
                    .DATA_TAP_SEL_DONE      (data_tap_select[1]),
                    .DQS_sel_done           (dqs_tap_sel_done[1]),
                    .VALID_DATA_TAP_COUNT   (valid_tap_count[1]),
                    .DATA_TAP_COUNT         (data_tap_count1[5:0])
                                );



endmodule