mem_interface_top_backend_rom_0.txt

DDR_SDRAM_verilog.rar

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_backend_rom_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: It instantiates the addr_gen and the data_gen modules. It takes
//              the user data stored in internal FIFOs and gives the data that
//              is to be compared with the read data.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

 module mem_interface_top_backend_rom_0
   (
    input                                clk0,
    input                                rst,
    input                                bkend_data_en,
    input                                bkend_wraddr_en,
    input                                bkend_rd_data_valid,

    output [35:0]                        app_af_addr,
    output                               app_af_WrEn,
    output [(`data_width*2)-1:0]         app_Wdf_data,
    output [(`data_mask_width*2)-1:0]    app_mask_data,
    output [(`data_width*2)-1:0]         app_compare_data,
    output                               app_Wdf_WrEn
    );


   wire [`fifo_16-1:0]                   app_Wdf_WrEn_w;

   wire [31:0]app_Wdf_data0;
wire [31:0]app_Wdf_data1;
wire [31:0]app_Wdf_data2;
wire [31:0]app_Wdf_data3;
   

   wire [3:0]app_mask_data0;
wire [3:0]app_mask_data1;
wire [3:0]app_mask_data2;
wire [3:0]app_mask_data3;
   

   wire [31:0]app_compare_data0;
wire [31:0]app_compare_data1;
wire [31:0]app_compare_data2;
wire [31:0]app_compare_data3;
   

   assign app_Wdf_data = {
                          app_Wdf_data3[31:16],app_Wdf_data2[31:16],app_Wdf_data1[31:16],app_Wdf_data0[31:16],
                          
                          app_Wdf_data3[15:0],app_Wdf_data2[15:0],app_Wdf_data1[15:0],app_Wdf_data0[15:0] };

   assign app_mask_data = {
                           app_mask_data3[3:2],app_mask_data2[3:2],app_mask_data1[3:2],app_mask_data0[3:2],
                           
                           app_mask_data3[1:0],app_mask_data2[1:0],app_mask_data1[1:0],app_mask_data0[1:0]};

   assign app_compare_data = {
                              app_compare_data3[31:16],app_compare_data2[31:16],app_compare_data1[31:16],app_compare_data0[31:16] ,
                              
                              app_compare_data3[15:0],app_compare_data2[15:0],app_compare_data1[15:0],app_compare_data0[15:0]};


   assign app_Wdf_WrEn = app_Wdf_WrEn_w[0];


   mem_interface_top_addr_gen addr_gen0
     (
      .clk0                (clk0),
      .rst                 (rst),
      .bkend_wraddr_en     (bkend_wraddr_en),
      .app_af_addr         (app_af_addr),
      .app_af_WrEn         (app_af_WrEn)
      );
   

   mem_interface_top_data_gen_16 data_gen_160
                   (
                    .clk0               (clk0),
                    .rst                (rst),
                    .bkend_data_en      (bkend_data_en),
                    .bkend_rd_data_valid(bkend_rd_data_valid),
                    .app_Wdf_data       (app_Wdf_data0[31:0]),
                    .app_mask_data      (app_mask_data0[3:0]),
                    .app_compare_data   (app_compare_data0[31:0]),
                    .app_Wdf_WrEn       (app_Wdf_WrEn_w[0])
                    );


mem_interface_top_data_gen_16 data_gen_161
                   (
                    .clk0               (clk0),
                    .rst                (rst),
                    .bkend_data_en      (bkend_data_en),
                    .bkend_rd_data_valid(bkend_rd_data_valid),
                    .app_Wdf_data       (app_Wdf_data1[31:0]),
                    .app_mask_data      (app_mask_data1[3:0]),
                    .app_compare_data   (app_compare_data1[31:0]),
                    .app_Wdf_WrEn       (app_Wdf_WrEn_w[1])
                    );


mem_interface_top_data_gen_16 data_gen_162
                   (
                    .clk0               (clk0),
                    .rst                (rst),
                    .bkend_data_en      (bkend_data_en),
                    .bkend_rd_data_valid(bkend_rd_data_valid),
                    .app_Wdf_data       (app_Wdf_data2[31:0]),
                    .app_mask_data      (app_mask_data2[3:0]),
                    .app_compare_data   (app_compare_data2[31:0]),
                    .app_Wdf_WrEn       (app_Wdf_WrEn_w[2])
                    );


mem_interface_top_data_gen_16 data_gen_163
                   (
                    .clk0               (clk0),
                    .rst                (rst),
                    .bkend_data_en      (bkend_data_en),
                    .bkend_rd_data_valid(bkend_rd_data_valid),
                    .app_Wdf_data       (app_Wdf_data3[31:0]),
                    .app_mask_data      (app_mask_data3[3:0]),
                    .app_compare_data   (app_compare_data3[31:0]),
                    .app_Wdf_WrEn       (app_Wdf_WrEn_w[3])
                    );


   

endmodule