mem_interface_top_rd_data_0.txt

DDR_SDRAM_verilog.rar

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_rd_data_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: The delay between the read data with respect to the command 
//              issued is calculted in terms of no. of clocks. This data is
//              then stored into the FIFOs and then read back and given as 
//              the ouput for comparison.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_rd_data_0
  (
   input                     CLK,
   input                     RESET,
   input                     ctrl_rden,
   input [`data_width-1:0]   READ_DATA_RISE,
   input [`data_width-1:0]   READ_DATA_FALL,
   output                    READ_DATA_VALID,
   output                    comp_done,
   output [`data_width-1:0]  READ_DATA_FIFO_RISE,
   output [`data_width-1:0]  READ_DATA_FIFO_FALL
   );


   reg [`ReadEnable-1:0]     rd_en_r1;
   reg [`ReadEnable-1:0]     rd_en_r2;
   reg [`ReadEnable-1:0]     rd_en_r3;
   reg [`ReadEnable-1:0]     rd_en_r4;
   reg [`ReadEnable-1:0]     rd_en_r5;
   reg [`ReadEnable-1:0]     rd_en_r6;
   reg [`ReadEnable-1:0]     rd_en_r7;
   reg                       comp_done_r;
   reg                       comp_done_r1;
   reg                       comp_done_r2;
   reg                       rst_r;
   reg [`data_strobe_width-1:0] rd_en_rise ;
   reg [`data_strobe_width-1:0] rd_en_fall ;
   reg                          fifo_rd_enable;
   reg                          fifo_rd_enable1;
   wire [`ReadEnable-1:0]       ctrl_rden1;
   wire [`ReadEnable-1:0]       first_rising_rden ;
   wire comp_done_0; 
wire comp_done_1; 
   wire [2:0] rise_clk_count0;
wire [2:0] fall_clk_count0;

wire [2:0] rise_clk_count1;
wire [2:0] fall_clk_count1;


   
  wire  read_data_valid0;
  

  wire  read_data_valid1;
  

  wire  read_data_valid2;
  

  wire  read_data_valid3;
  

  wire  read_data_valid4;
  

  wire  read_data_valid5;
  

  wire  read_data_valid6;
  

  wire  read_data_valid7;
  

   assign    ctrl_rden1 = { ctrl_rden , ctrl_rden };
   assign    READ_DATA_VALID = read_data_valid0;

   mem_interface_top_pattern_compare8 pattern_0
        ( .clk              (CLK),
          .rst              (RESET),
          .ctrl_rden        (ctrl_rden1[0]),
          .rd_data_rise     (READ_DATA_RISE[31 : 24]),
          .rd_data_fall     (READ_DATA_FALL[31 : 24]),
          .comp_done        (comp_done_0),
          .first_rising     (first_rising_rden[0]),
          .rise_clk_count   (rise_clk_count0),
          .fall_clk_count   (fall_clk_count0)
        );


mem_interface_top_pattern_compare8 pattern_1
        ( .clk              (CLK),
          .rst              (RESET),
          .ctrl_rden        (ctrl_rden1[1]),
          .rd_data_rise     (READ_DATA_RISE[63 : 56]),
          .rd_data_fall     (READ_DATA_FALL[63 : 56]),
          .comp_done        (comp_done_1),
          .first_rising     (first_rising_rden[1]),
          .rise_clk_count   (rise_clk_count1),
          .fall_clk_count   (fall_clk_count1)
        );



   always @( posedge CLK )
     rst_r <= RESET;

   always @(posedge CLK) begin
      if(rst_r)
        begin
           rd_en_r1 <= `ReadEnable'h0;
           rd_en_r2 <= `ReadEnable'h0;
           rd_en_r3 <= `ReadEnable'h0;
           rd_en_r4 <= `ReadEnable'h0;
           rd_en_r5 <= `ReadEnable'h0;
           rd_en_r6 <= `ReadEnable'h0;
           rd_en_r7 <= `ReadEnable'h0;
        end
      else
        begin
           rd_en_r1 <= ctrl_rden1;
           rd_en_r2 <= rd_en_r1;
           rd_en_r3 <= rd_en_r2;
           rd_en_r4 <= rd_en_r3;
           rd_en_r5 <= rd_en_r4;
           rd_en_r6 <= rd_en_r5;
           rd_en_r7 <= rd_en_r6;
        end
   end

   always @(posedge CLK) begin
      if(rst_r)
        begin
           comp_done_r  <= 1'b0;
           comp_done_r1 <= 1'b0;
           comp_done_r2 <= 1'b0;
        end
      else
        begin
           comp_done_r  <=  comp_done_0 && comp_done_1  ;
           comp_done_r1 <= comp_done_r;
           comp_done_r2 <= comp_done_r1;
        end
   end

   assign comp_done = (rst_r == 1'b1) ? 1'b0 :  comp_done_0 && comp_done_1  ;

   
always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[0] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count0)
    3'b011 :
        rd_en_rise[0] <= rd_en_r2[0];

    3'b100 :
        rd_en_rise[0] <= rd_en_r3[0];

    3'b101:
        rd_en_rise[0] <= rd_en_r4[0];

    3'b110:
        rd_en_rise[0] <= rd_en_r5[0];

    3'b111:
        rd_en_rise[0] <= rd_en_r6[0];

    default :
        rd_en_rise[0] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[0] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count0)
    3'b011 :
        rd_en_fall[0] <= rd_en_r2[0];

    3'b100 :
        rd_en_fall[0] <= rd_en_r3[0];

    3'b101:
        rd_en_fall[0] <= rd_en_r4[0];

    3'b110:
        rd_en_fall[0] <= rd_en_r5[0];

    3'b111:
        rd_en_fall[0] <= rd_en_r6[0];

    default :
        rd_en_fall[0] <= 1'b0;
  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[1] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count0)
    3'b011 :
        rd_en_rise[1] <= rd_en_r2[0];

    3'b100 :
        rd_en_rise[1] <= rd_en_r3[0];

    3'b101:
        rd_en_rise[1] <= rd_en_r4[0];

    3'b110:
        rd_en_rise[1] <= rd_en_r5[0];

    3'b111:
        rd_en_rise[1] <= rd_en_r6[0];

    default :
        rd_en_rise[1] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[1] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count0)
    3'b011 :
        rd_en_fall[1] <= rd_en_r2[0];

    3'b100 :
        rd_en_fall[1] <= rd_en_r3[0];

    3'b101:
        rd_en_fall[1] <= rd_en_r4[0];

    3'b110:
        rd_en_fall[1] <= rd_en_r5[0];

    3'b111:
        rd_en_fall[1] <= rd_en_r6[0];

    default :
        rd_en_fall[1] <= 1'b0;
  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[2] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count0)
    3'b011 :
        rd_en_rise[2] <= rd_en_r2[0];

    3'b100 :
        rd_en_rise[2] <= rd_en_r3[0];

    3'b101:
        rd_en_rise[2] <= rd_en_r4[0];

    3'b110:
        rd_en_rise[2] <= rd_en_r5[0];

    3'b111:
        rd_en_rise[2] <= rd_en_r6[0];

    default :
        rd_en_rise[2] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[2] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count0)
    3'b011 :
        rd_en_fall[2] <= rd_en_r2[0];

    3'b100 :
        rd_en_fall[2] <= rd_en_r3[0];

    3'b101:
        rd_en_fall[2] <= rd_en_r4[0];

    3'b110:
        rd_en_fall[2] <= rd_en_r5[0];

    3'b111:
        rd_en_fall[2] <= rd_en_r6[0];

    default :
        rd_en_fall[2] <= 1'b0;
  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[3] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count0)
    3'b011 :
        rd_en_rise[3] <= rd_en_r2[0];

    3'b100 :
        rd_en_rise[3] <= rd_en_r3[0];

    3'b101:
        rd_en_rise[3] <= rd_en_r4[0];

    3'b110:
        rd_en_rise[3] <= rd_en_r5[0];

    3'b111:
        rd_en_rise[3] <= rd_en_r6[0];

    default :
        rd_en_rise[3] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[3] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count0)
    3'b011 :
        rd_en_fall[3] <= rd_en_r2[0];

    3'b100 :
        rd_en_fall[3] <= rd_en_r3[0];

    3'b101:
        rd_en_fall[3] <= rd_en_r4[0];

    3'b110:
        rd_en_fall[3] <= rd_en_r5[0];

    3'b111:
        rd_en_fall[3] <= rd_en_r6[0];

    default :
        rd_en_fall[3] <= 1'b0;