full_1c20.v

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

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//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module DSR_pio_s1_arbitrator (
                               // inputs:
                                clk,
                                cpu_data_master_address_to_slave,
                                cpu_data_master_read,
                                cpu_data_master_waitrequest,
                                cpu_data_master_write,
                                cpu_data_master_writedata,
                                reset_n,

                               // outputs:
                                DSR_pio_s1_address,
                                DSR_pio_s1_chipselect,
                                DSR_pio_s1_reset_n,
                                DSR_pio_s1_write_n,
                                DSR_pio_s1_writedata,
                                cpu_data_master_granted_DSR_pio_s1,
                                cpu_data_master_qualified_request_DSR_pio_s1,
                                cpu_data_master_read_data_valid_DSR_pio_s1,
                                cpu_data_master_requests_DSR_pio_s1,
                                d1_DSR_pio_s1_end_xfer
                             );

  output  [  1: 0] DSR_pio_s1_address;
  output           DSR_pio_s1_chipselect;
  output           DSR_pio_s1_reset_n;
  output           DSR_pio_s1_write_n;
  output           DSR_pio_s1_writedata;
  output           cpu_data_master_granted_DSR_pio_s1;
  output           cpu_data_master_qualified_request_DSR_pio_s1;
  output           cpu_data_master_read_data_valid_DSR_pio_s1;
  output           cpu_data_master_requests_DSR_pio_s1;
  output           d1_DSR_pio_s1_end_xfer;
  input            clk;
  input   [ 25: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] DSR_pio_s1_address;
  wire             DSR_pio_s1_allgrants;
  wire             DSR_pio_s1_allow_new_arb_cycle;
  wire             DSR_pio_s1_any_continuerequest;
  wire             DSR_pio_s1_arb_counter_enable;
  reg     [  2: 0] DSR_pio_s1_arb_share_counter;
  wire    [  2: 0] DSR_pio_s1_arb_share_counter_next_value;
  wire    [  2: 0] DSR_pio_s1_arb_share_set_values;
  wire             DSR_pio_s1_arbitration_holdoff_internal;
  wire             DSR_pio_s1_beginbursttransfer_internal;
  wire             DSR_pio_s1_begins_xfer;
  wire             DSR_pio_s1_chipselect;
  wire             DSR_pio_s1_end_xfer;
  wire             DSR_pio_s1_firsttransfer;
  wire             DSR_pio_s1_grant_vector;
  wire             DSR_pio_s1_in_a_read_cycle;
  wire             DSR_pio_s1_in_a_write_cycle;
  wire             DSR_pio_s1_master_qreq_vector;
  wire             DSR_pio_s1_reset_n;
  reg              DSR_pio_s1_slavearbiterlockenable;
  wire             DSR_pio_s1_waits_for_read;
  wire             DSR_pio_s1_waits_for_write;
  wire             DSR_pio_s1_write_n;
  wire             DSR_pio_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_DSR_pio_s1;
  wire             cpu_data_master_qualified_request_DSR_pio_s1;
  wire             cpu_data_master_read_data_valid_DSR_pio_s1;
  wire             cpu_data_master_requests_DSR_pio_s1;
  wire             cpu_data_master_saved_grant_DSR_pio_s1;
  reg              d1_DSR_pio_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_DSR_pio_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~DSR_pio_s1_end_xfer;
    end


  assign DSR_pio_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_DSR_pio_s1));
  assign cpu_data_master_requests_DSR_pio_s1 = ({cpu_data_master_address_to_slave[25 : 4] , 4'b0} == 26'h8110f0) & (cpu_data_master_read | cpu_data_master_write);
  //DSR_pio_s1_arb_share_counter set values, which is an e_mux
  assign DSR_pio_s1_arb_share_set_values = 1;

  //DSR_pio_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign DSR_pio_s1_arb_share_counter_next_value = DSR_pio_s1_firsttransfer ? (DSR_pio_s1_arb_share_set_values - 1) : |DSR_pio_s1_arb_share_counter ? (DSR_pio_s1_arb_share_counter - 1) : 0;

  //DSR_pio_s1_allgrants all slave grants, which is an e_mux
  assign DSR_pio_s1_allgrants = |DSR_pio_s1_grant_vector;

  //DSR_pio_s1_end_xfer assignment, which is an e_assign
  assign DSR_pio_s1_end_xfer = ~(DSR_pio_s1_waits_for_read | DSR_pio_s1_waits_for_write);

  //DSR_pio_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign DSR_pio_s1_arb_counter_enable = DSR_pio_s1_end_xfer & DSR_pio_s1_allgrants;

  //DSR_pio_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          DSR_pio_s1_arb_share_counter <= 0;
      else if (DSR_pio_s1_arb_counter_enable)
          DSR_pio_s1_arb_share_counter <= DSR_pio_s1_arb_share_counter_next_value;
    end


  //DSR_pio_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          DSR_pio_s1_slavearbiterlockenable <= 0;
      else if (|DSR_pio_s1_master_qreq_vector & DSR_pio_s1_end_xfer)
          DSR_pio_s1_slavearbiterlockenable <= |DSR_pio_s1_arb_share_counter_next_value;
    end


  //cpu/data_master DSR_pio/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = DSR_pio_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //DSR_pio_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign DSR_pio_s1_any_continuerequest = 0;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 0;

  assign cpu_data_master_qualified_request_DSR_pio_s1 = cpu_data_master_requests_DSR_pio_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //DSR_pio_s1_writedata mux, which is an e_mux
  assign DSR_pio_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_DSR_pio_s1 = cpu_data_master_qualified_request_DSR_pio_s1;

  //cpu/data_master saved-grant DSR_pio/s1, which is an e_assign
  assign cpu_data_master_saved_grant_DSR_pio_s1 = cpu_data_master_requests_DSR_pio_s1;

  //allow new arb cycle for DSR_pio/s1, which is an e_assign
  assign DSR_pio_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign DSR_pio_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign DSR_pio_s1_master_qreq_vector = 1;

  //DSR_pio_s1_reset_n assignment, which is an e_assign
  assign DSR_pio_s1_reset_n = reset_n;

  assign DSR_pio_s1_chipselect = cpu_data_master_granted_DSR_pio_s1;
  //DSR_pio_s1_firsttransfer first transaction, which is an e_assign
  assign DSR_pio_s1_firsttransfer = ~(DSR_pio_s1_slavearbiterlockenable & DSR_pio_s1_any_continuerequest);

  //DSR_pio_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign DSR_pio_s1_beginbursttransfer_internal = DSR_pio_s1_begins_xfer & DSR_pio_s1_firsttransfer;

  //DSR_pio_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign DSR_pio_s1_arbitration_holdoff_internal = DSR_pio_s1_begins_xfer & DSR_pio_s1_firsttransfer;

  //~DSR_pio_s1_write_n assignment, which is an e_mux
  assign DSR_pio_s1_write_n = ~(cpu_data_master_granted_DSR_pio_s1 & cpu_data_master_write);

  //DSR_pio_s1_address mux, which is an e_mux
  assign DSR_pio_s1_address = cpu_data_master_address_to_slave >> 2;

  //d1_DSR_pio_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_DSR_pio_s1_end_xfer <= 1;
      else if (1)
          d1_DSR_pio_s1_end_xfer <= DSR_pio_s1_end_xfer;
    end


  //DSR_pio_s1_waits_for_read in a cycle, which is an e_mux
  assign DSR_pio_s1_waits_for_read = DSR_pio_s1_in_a_read_cycle & DSR_pio_s1_begins_xfer;

  //DSR_pio_s1_in_a_read_cycle assignment, which is an e_assign
  assign DSR_pio_s1_in_a_read_cycle = cpu_data_master_granted_DSR_pio_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = DSR_pio_s1_in_a_read_cycle;

  //DSR_pio_s1_waits_for_write in a cycle, which is an e_mux
  assign DSR_pio_s1_waits_for_write = DSR_pio_s1_in_a_write_cycle & 0;

  //DSR_pio_s1_in_a_write_cycle assignment, which is an e_assign
  assign DSR_pio_s1_in_a_write_cycle = cpu_data_master_granted_DSR_pio_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = DSR_pio_s1_in_a_write_cycle;

  assign wait_for_DSR_pio_s1_counter = 0;

  // synthesis attribute DSR_pio_s1_arbitrator auto_dissolve FALSE

endmodule


module alarm_pio_s1_arbitrator (
                                 // inputs:
                                  clk,
                                  cpu_data_master_address_to_slave,
                                  cpu_data_master_read,
                                  cpu_data_master_waitrequest,