pc.edf

键盘和USB与PC机的接口程序

(edif PC
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 1999 2 18 2 12 14)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "5.0.7"))
     )
   )
  (external lattice
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell XBIDI1 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port XB0 (direction INOUT))
           (port A0 (direction INPUT))
           (port OE (direction INPUT))
         )
       )
    )
    (cell XINPUT (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port XI0 (direction INPUT))
         )
       )
    )
    (cell XOUTPUT (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port XO0 (direction OUTPUT))
           (port A0 (direction INPUT))
         )
       )
    )
    (cell DFF_FD (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port CP (direction INPUT))
           (port R (direction INPUT))
         )
       )
    )
    (cell OR2 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
         )
       )
    )
    (cell AND2 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port ZN0 (direction OUTPUT))
           (port A0 (direction INPUT))
         )
       )
    )
    (cell BI11 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port XB0 (direction INOUT))
           (port A0 (direction INPUT))
           (port OE (direction INPUT))
         )
       )
    )
    (cell IB11 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port XI0 (direction INPUT))
         )
       )
    )
    (cell MUX2 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port S0 (direction INPUT))
         )
       )
    )
    (cell OB11 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port XO0 (direction OUTPUT))
           (port A0 (direction INPUT))
         )
       )
    )
    (cell FD21 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Q0 (direction OUTPUT))
           (port D0 (direction INPUT))
           (port CLK (direction INPUT))
           (port CD (direction INPUT))
         )
       )
    )
    (cell OR3 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
         )
       )
    )
    (cell AND3 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
         )
       )
    )
    (cell XOR3 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
         )
       )
    )
    (cell XOR2 (cellType GENERIC)
       (view prim (viewType NETLIST)
         (interface
           (port Z0 (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell PC (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port (array (rename ADDX_BUS "addx_bus[11:0]") 12) (direction OUTPUT))
           (port (array (rename DATA_BUS "data_bus[7:0]") 8) (direction INOUT))
           (port (array (rename PORT "port[7:0]") 8) (direction INOUT))
           (port sys_clk (direction INPUT))
           (port sys_rst (direction INPUT))
           (port code_cs_l (direction OUTPUT))