vania.gfl

A VHDL program to simulate the behaviour of a device,

# XST (Creating Lso File) : 
sreg8.lso
# xst flow : RunXST
sreg8.syr
sreg8.prj
sreg8.sprj
sreg8.ana
sreg8.stx
sreg8.cmd_log
sreg8.ngc
sreg8.ngr
# View RTL Schematic
sreg8.ngr
# XST (Creating Lso File) : 
project.lso
# xst flow : RunXST
project.syr
project.prj
project.sprj
project.ana
project.stx
project.cmd_log
sreg8.ngc
sreg8.ngr
project.ngr
# View RTL Schematic
project.ngr
# ProjNav -> New Source -> TBW
D:\CShT\Vania\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
reg8.lso
# xst flow : RunXST
reg8.syr
reg8.prj
reg8.sprj
reg8.ana
reg8.stx
reg8.cmd_log
reg8.ngc
reg8.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\vania/_ngo
reg8.ngd
reg8_ngdbuild.nav
reg8.bld
.untf
reg8.cmd_log
# Implementation : Map
reg8_map.ncd
reg8.ngm
reg8.pcf
reg8.nc1
reg8.mrp
reg8_map.mrp
reg8.mdf
__projnav/map.log
reg8.cmd_log
MAP_NO_GUIDE_FILE_CPF "reg8"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
reg8.twr
reg8.twx
reg8.tsi
reg8.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
reg8.ncd
reg8.par
reg8.pad
reg8_pad.txt
reg8_pad.csv
reg8.pad_txt
reg8.dly
reportgen.log
reg8.xpi
reg8.grf
reg8.itr
reg8_last_par.ncd
__projnav/par.log
reg8.placed_ncd_tracker
reg8.routed_ncd_tracker
reg8.cmd_log
PAR_NO_GUIDE_FILE_CPF "reg8"
# Implementation : Generate Post-Par Simulation Model
reg8_timesim.vhd
reg8_timesim.sdf
reg8_timesim.sdf
reg8_timesim.vhd
reg8_timesim.nlf
reg8.par_nlf
reg8.vhdsim_par
reg8.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test_reg8.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_reg8.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Vania\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
buf8.lso
# xst flow : RunXST
buf8.syr
buf8.prj
buf8.sprj
buf8.ana
buf8.stx
buf8.cmd_log
buf8.ngc
buf8.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\vania/_ngo
buf8.ngd
buf8_ngdbuild.nav
buf8.bld
.untf
buf8.cmd_log
# Implementation : Map
buf8_map.ncd
buf8.ngm
buf8.pcf
buf8.nc1
buf8.mrp
buf8_map.mrp
buf8.mdf
__projnav/map.log
buf8.cmd_log
MAP_NO_GUIDE_FILE_CPF "buf8"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
buf8.twr
buf8.twx
buf8.tsi
buf8.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
buf8.ncd
buf8.par
buf8.pad
buf8_pad.txt
buf8_pad.csv
buf8.pad_txt
buf8.dly
reportgen.log
buf8.xpi
buf8.grf
buf8.itr
buf8_last_par.ncd
__projnav/par.log
buf8.placed_ncd_tracker
buf8.routed_ncd_tracker
buf8.cmd_log
PAR_NO_GUIDE_FILE_CPF "buf8"
# Implementation : Generate Post-Par Simulation Model
buf8_timesim.vhd
buf8_timesim.sdf
buf8_timesim.sdf
buf8_timesim.vhd
buf8_timesim.nlf
buf8.par_nlf
buf8.vhdsim_par
buf8.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test_buf.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_buf.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Vania\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
dec2to4.lso
# xst flow : RunXST
dec2to4.syr
dec2to4.prj
dec2to4.sprj
dec2to4.ana
dec2to4.stx
dec2to4.cmd_log
dec2to4.ngc
dec2to4.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\vania/_ngo
dec2to4.ngd
dec2to4_ngdbuild.nav
dec2to4.bld
.untf
dec2to4.cmd_log
# Implementation : Map
dec2to4_map.ncd
dec2to4.ngm
dec2to4.pcf
dec2to4.nc1
dec2to4.mrp
dec2to4_map.mrp
dec2to4.mdf
__projnav/map.log
dec2to4.cmd_log
MAP_NO_GUIDE_FILE_CPF "dec2to4"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
dec2to4.twr
dec2to4.twx
dec2to4.tsi
dec2to4.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
dec2to4.ncd
dec2to4.par
dec2to4.pad
dec2to4_pad.txt
dec2to4_pad.csv
dec2to4.pad_txt
dec2to4.dly
reportgen.log
dec2to4.xpi
dec2to4.grf
dec2to4.itr
dec2to4_last_par.ncd
__projnav/par.log
dec2to4.placed_ncd_tracker
dec2to4.routed_ncd_tracker
dec2to4.cmd_log
PAR_NO_GUIDE_FILE_CPF "dec2to4"
# Implementation : Generate Post-Par Simulation Model
dec2to4_timesim.vhd
dec2to4_timesim.sdf
dec2to4_timesim.sdf
dec2to4_timesim.vhd
dec2to4_timesim.nlf
dec2to4.par_nlf
dec2to4.vhdsim_par
dec2to4.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test_dec.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_dec.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Vania\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\vania/_ngo
sreg8.ngd
sreg8_ngdbuild.nav
sreg8.bld
.untf
sreg8.cmd_log
# Implementation : Map
sreg8_map.ncd
sreg8.ngm
sreg8.pcf
sreg8.nc1
sreg8.mrp
sreg8_map.mrp
sreg8.mdf
__projnav/map.log
sreg8.cmd_log
MAP_NO_GUIDE_FILE_CPF "sreg8"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
sreg8.twr
sreg8.twx
sreg8.tsi
sreg8.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
sreg8.ncd
sreg8.par
sreg8.pad
sreg8_pad.txt
sreg8_pad.csv
sreg8.pad_txt
sreg8.dly
reportgen.log
sreg8.xpi
sreg8.grf
sreg8.itr
sreg8_last_par.ncd
__projnav/par.log
sreg8.placed_ncd_tracker
sreg8.routed_ncd_tracker
sreg8.cmd_log
PAR_NO_GUIDE_FILE_CPF "sreg8"
# Implementation : Generate Post-Par Simulation Model
sreg8_timesim.vhd
sreg8_timesim.sdf
sreg8_timesim.sdf
sreg8_timesim.vhd
sreg8_timesim.nlf
sreg8.par_nlf
sreg8.vhdsim_par
sreg8.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test_sreg8.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_sreg8.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_sreg8.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_sreg8.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_sreg8.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_sreg8.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_sreg8.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_sreg8.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Vania\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
project.syr
project.prj
project.sprj
project.ana
project.stx
project.cmd_log
sreg8.ngc
reg8.ngc
buf8.ngc
dec2to4.ngc
project.ngc
sreg8.ngr
reg8.ngr
buf8.ngr
dec2to4.ngr
project.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\vania/_ngo
project.ngd
project_ngdbuild.nav
project.bld
.untf
project.cmd_log
# Implementation : Map
project_map.ncd
project.ngm
project.pcf
project.nc1
project.mrp
project_map.mrp
project.mdf
__projnav/map.log
project.cmd_log
MAP_NO_GUIDE_FILE_CPF "project"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
project.twr
project.twx
project.tsi
project.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
project.ncd
project.par
project.pad
project_pad.txt
project_pad.csv
project.pad_txt
project.dly
reportgen.log
project.xpi
project.grf
project.itr
project_last_par.ncd
__projnav/par.log
project.placed_ncd_tracker
project.routed_ncd_tracker
project.cmd_log
PAR_NO_GUIDE_FILE_CPF "project"
# Implementation : Generate Post-Par Simulation Model
project_timesim.vhd
project_timesim.sdf
project_timesim.sdf
project_timesim.vhd
project_timesim.nlf
project.par_nlf
project.vhdsim_par
project.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test_all.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_all.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_all.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_all.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_all.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_all.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_all.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_all.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test_all.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_all.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Assign Package Pins Post-Translate
__projnav/xlatePace.rsp
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
project.mfp
# Implementation : Analyze Power (XPower)
project.cxt
# Implmentation : Back-annotate Pin Locations
__projnav/ncdTOlck_tcl.rsp
project_last_ngd.ngd
project_last_ngd_report.bld
project.lck
project.lpc
project.cmd_log
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
project.mfp
# Implmentation : Floorplan Design Post-Map (Floorplanner)
__projnav/mapFloorPlanner.rsp
project_map.mfp
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Assign Package Pins Post-Translate
__projnav/xlatePace.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
and_ent.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
buf8.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
dec2to4.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
or1_ent.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
or2_ent.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
reg8.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
sreg8.spl
__projnav/vhd2spl.err
# Schematic : PDCL (jhdparse)
__projnav/schema_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/schema_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/schema_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/schema_jhdparse_tcl.rsp
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
project.spl
__projnav/vhd2spl.err
# Schematic : PDCL (jhdparse)
__projnav/opit_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/opit_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/opit_jhdparse_tcl.rsp