hdpdeps.ref

A VHDL program to simulate the behaviour of a device,

V1 39
FL d:/csht/vania/dec2to4.vhd 2007/05/21.17:49:33
FL D:/CShT/Vania/buf8.vhd 2007/05/21.17:48:59
EN work/BUF8            FL D:/CShT/Vania/buf8.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/BUF8/BEHAVIORAL FL D:/CShT/Vania/buf8.vhd EN work/BUF8
FL D:/CShT/Vania/sreg8.vhd 2007/05/21.17:51:40
EN work/SREG8           FL D:/CShT/Vania/sreg8.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/SREG8/BEHAVIORAL FL D:/CShT/Vania/sreg8.vhd EN work/SREG8
FL d:/csht/vania/sreg8.vhd 2007/05/21.17:51:40
FL D:/CShT/Vania/and_ent.vhd 2007/05/21.17:48:17
EN work/AND_ENT         FL D:/CShT/Vania/and_ent.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/AND_ENT/BEHAVIORAL FL D:/CShT/Vania/and_ent.vhd EN work/AND_ENT
FL d:/csht/vania/or1_ent.vhd 2007/05/21.17:49:59
FL D:/CShT/Vania/project.vhd 2007/05/21.17:47:38
EN work/PROJECT         FL D:/CShT/Vania/project.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/PROJECT/STRUCTURAL FL D:/CShT/Vania/project.vhd EN work/PROJECT CP SREG8 \
      CP REG8           CP BUF8           CP DEC2TO4        CP OR1_ENT        CP OR2_ENT \
      CP AND_ENT
FL d:/csht/vania/reg8.vhd 2007/05/21.17:51:04
FL d:/csht/vania/or2_ent.vhd 2007/05/21.17:50:26
FL D:/CShT/Vania/dec2to4.vhd 2007/05/21.17:49:33
EN work/DEC2TO4         FL D:/CShT/Vania/dec2to4.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DEC2TO4/BEHAVIORAL FL D:/CShT/Vania/dec2to4.vhd EN work/DEC2TO4
FL D:/CShT/Vania/reg8.vhd 2007/05/21.17:51:04
EN work/REG8            FL D:/CShT/Vania/reg8.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/REG8/BEHAVIORAL FL D:/CShT/Vania/reg8.vhd EN work/REG8
FL d:/csht/vania/and_ent.vhd 2007/05/21.17:48:17
FL D:/CShT/Vania/or1_ent.vhd 2007/05/21.17:49:59
EN work/OR1_ENT         FL D:/CShT/Vania/or1_ent.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/OR1_ENT/BEHAVIORAL FL D:/CShT/Vania/or1_ent.vhd EN work/OR1_ENT
FL d:/csht/vania/project.vhd 2007/05/21.17:47:38
FL D:/CShT/Vania/or2_ent.vhd 2007/05/21.17:50:26
EN work/OR2_ENT         FL D:/CShT/Vania/or2_ent.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/OR2_ENT/BEHAVIORAL FL D:/CShT/Vania/or2_ent.vhd EN work/OR2_ENT
FL d:/csht/vania/buf8.vhd 2007/05/21.17:48:59