hdllib.ref

A VHDL program to simulate the behaviour of a device,

AR reg8 behavioral D:/CShT/Vania/reg8.vhd sub00/vhpl03
EN or2_ent NULL D:/CShT/Vania/or2_ent.vhd sub00/vhpl10
AR and_ent behavioral D:/CShT/Vania/and_ent.vhd sub00/vhpl13
EN sreg8 NULL D:/CShT/Vania/sreg8.vhd sub00/vhpl00
AR project structural D:/CShT/Vania/project.vhd sub00/vhpl15
EN dec2to4 NULL D:/CShT/Vania/dec2to4.vhd sub00/vhpl06
AR or1_ent behavioral D:/CShT/Vania/or1_ent.vhd sub00/vhpl09
EN buf8 NULL D:/CShT/Vania/buf8.vhd sub00/vhpl04
EN project NULL D:/CShT/Vania/project.vhd sub00/vhpl14
AR buf8 behavioral D:/CShT/Vania/buf8.vhd sub00/vhpl05
AR sreg8 behavioral D:/CShT/Vania/sreg8.vhd sub00/vhpl01
EN reg8 NULL D:/CShT/Vania/reg8.vhd sub00/vhpl02
AR dec2to4 behavioral D:/CShT/Vania/dec2to4.vhd sub00/vhpl07
EN and_ent NULL D:/CShT/Vania/and_ent.vhd sub00/vhpl12
AR or2_ent behavioral D:/CShT/Vania/or2_ent.vhd sub00/vhpl11
EN or1_ent NULL D:/CShT/Vania/or1_ent.vhd sub00/vhpl08