📄 testproject.timesim_vhw
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-- D:\CSHT\FINAL15.06.07\PROJECT\IMPORTANTVERSION
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Jun 26 13:11:46 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY testProject IS
END testProject;
ARCHITECTURE testbench_arch OF testProject IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT project
PORT (
A : In std_logic_vector (1 DOWNTO 0);
SDATA : In std_logic;
SCLK : In std_logic;
RESET : In std_logic;
WR : In std_logic;
RD : In std_logic;
D : Out std_logic_vector (7 DOWNTO 0);
REG_OUT : InOut std_logic_vector (7 DOWNTO 0);
IRQ : Out std_logic
);
END COMPONENT;
SIGNAL A : std_logic_vector (1 DOWNTO 0);
SIGNAL SDATA : std_logic;
SIGNAL SCLK : std_logic;
SIGNAL RESET : std_logic;
SIGNAL WR : std_logic;
SIGNAL RD : std_logic;
SIGNAL D : std_logic_vector (7 DOWNTO 0);
SIGNAL REG_OUT : std_logic_vector (7 DOWNTO 0);
SIGNAL IRQ : std_logic;
BEGIN
UUT : project
PORT MAP (
A => A,
SDATA => SDATA,
SCLK => SCLK,
RESET => RESET,
WR => WR,
RD => RD,
D => D,
REG_OUT => REG_OUT,
IRQ => IRQ
);
PROCESS -- clock process for SCLK,
BEGIN
CLOCK_LOOP : LOOP
SCLK <= transport '0';
WAIT FOR 10 ns;
SCLK <= transport '1';
WAIT FOR 10 ns;
WAIT FOR 40 ns;
SCLK <= transport '0';
WAIT FOR 40 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for SCLK
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_D(
next_D : std_logic_vector (7 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (D /= next_D) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns D="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_D);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_IRQ(
next_IRQ : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (IRQ /= next_IRQ) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns IRQ="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, IRQ);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_IRQ);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_REG_OUT(
next_REG_OUT : std_logic_vector (7 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (REG_OUT /= next_REG_OUT) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns REG_OUT="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, REG_OUT);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_REG_OUT);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
A <= transport std_logic_vector'("00"); --0
SDATA <= transport '0';
RESET <= transport '0';
WR <= transport '0';
RD <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
RESET <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
SDATA <= transport '1';
WR <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
SDATA <= transport '0';
-- --------------------
WAIT FOR 200 ns; -- Time=500 ns
SDATA <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=600 ns
A <= transport std_logic_vector'("01"); --1
SDATA <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=700 ns
A <= transport std_logic_vector'("01"); --1
SDATA <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=800 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=900 ns
A <= transport std_logic_vector'("01"); --1
SDATA <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=1000 ns
A <= transport std_logic_vector'("01"); --1
SDATA <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=1100 ns
A <= transport std_logic_vector'("01"); --1
SDATA <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=1200 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1300 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1400 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1500 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1600 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1700 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1800 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1900 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=2000 ns
A <= transport std_logic_vector'("01"); --1
-- --------------------
WAIT FOR 110 ns; -- Time=2110 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION project_cfg OF testProject IS
FOR testbench_arch
END FOR;
END project_cfg;
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