testmachine.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testmachine is

	port( SCLK			  : in std_logic;
			START			  : in std_logic;
			TESTMODE		  : in std_logic;
			INDSTATE		  : out std_logic_vector(3 downto 0);
			D		        : inout std_logic_vector (7 downto 0);
			REG_OUT		  : inout std_logic_vector (7 downto 0);
			SDATA			  : inout std_logic;
			A 		        : inout std_logic_vector (1 downto 0);
			RESET   		  : inout std_logic ;
			WR 	        : inout std_logic;
			RD		        : inout std_logic;
			OKforCalc	  : out std_logic;
			OKforReset    : out std_logic;
			ResetIndy	  : out std_logic;
			ResetCalc     : inout std_logic
			);

end entity;

architecture Structural  of testmachine is

	 type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
	 signal state, nextstate : state_type;


begin
								
-----------------------------------------------------------
	 process1 : process (START, SCLK)
	 	begin
			if (START = '0') then state <=s0;			 
			elsif (SCLK ='1' and SCLK'event) then state <=nextstate;
			end if;
	 end process process1;

-------------------------------------------------------------------------
	 process2 : process (state, TESTMODE)
		begin
		 case state is 
		 	   when s0 => if TESTMODE = '1' then
									nextstate <=s1;
							  else
							  		nextstate <=s5;
							  end if;
				when s1 => nextstate <=s2;
				when s2 => nextstate <=s3;
				when s3 => nextstate <=s4;
				when s4 => nextstate <=s9;
				when s5 => nextstate <=s6;
				when s6 => nextstate <=s7;
				when s7 => nextstate <=s8;
				when s8 => nextstate <=s9;
				when s9 => nextstate <=s9;
			end case;
	 end process process2;

-------------------------------------------------------------------------
	 process3 : process (state,SCLK)
	 begin
	 			if(SCLK = '1' and SCLK'event ) then
					case state is 
						when s0=> INDSTATE<= "0000";
									 ResetCalc<= '0';
									 OKforCalc<= '0';
									 OKforReset<= '0';
									 ResetIndy<= '1';
									 A<= "00";
									 SDATA<= '0';
									 RESET<= '0';
									 WR<= '0';
									 RD<= '0';
						when s1=> INDSTATE<= "0001";
									 A<= "01";
									 SDATA<= '0';	
								 	 RESET<= '1';	 	
		 							 WR<= '1';
		 							 RD<= '0';				 
		 				when s2=> INDSTATE<= "0010";

		 				when s3=> INDSTATE<= "0011";
									 			
						when s4=> INDSTATE<= "0100";
									 
						when s5=> INDSTATE<= "0101";
									 ResetCalc<= '1';
						when s6=> INDSTATE<= "0110";

						when s7=> INDSTATE<= "0111";

						when s8=> INDSTATE<= "1000";
										
						when s9=> INDSTATE<= "1001";
									 ResetIndy<='0';
									 if (TESTMODE = '0') then
									 		if ( D/="UUUUUUUU" ) then OKforReset<= '1';
											end if;
								
									 else 
									 		if (D = "00000000") then OKforCalc<= '1'; 
										   end if;		
									  end if;
									
						end case;
					end if;



	 end process process3;


-------------------------------------------------------------------------
end Structural;