fsm.syr

VHDL source code for test machine.

	inferred   1 Finite State Machine(s).
	inferred  12 D-type flip-flop(s).
Unit <testmachine> synthesized.


Synthesizing Unit <fsm>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/fsm.vhd.
Unit <fsm> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Counters                         : 1
 23-bit up counter                 : 1
# Registers                        : 28
 2-bit register                    : 1
 1-bit register                    : 25
 4-bit register                    : 1
 8-bit register                    : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <A_1> (without init value) is constant in block <testmachine>.
WARNING:Xst:1291 - FF/Latch <RESET> is unconnected in block <test>.

Optimizing unit <fsm> ...

Optimizing unit <testmachine> ...
Loading device for application Xst from file '2v40.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <device_sreg_REG_0> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_1> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_2> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_3> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_4> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_5> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_6> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_7> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_8> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_5> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_4> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_3> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_2> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_1> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_0> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_7> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_6> (without init value) is constant in block <fsm>.
WARNING:Xst:1291 - FF/Latch <test_RESET> is unconnected in block <fsm>.
WARNING:Xst:1291 - FF/Latch <test_WR> is unconnected in block <fsm>.
WARNING:Xst:1291 - FF/Latch <test_ResetCalc> is unconnected in block <fsm>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fsm, actual ratio is 9.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fsm.ngr
Top Level Output File Name         : fsm
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 22

Macro Statistics :
# Registers                        : 19
#      1-bit register              : 15
#      2-bit register              : 1
#      23-bit register             : 1
#      4-bit register              : 1
#      8-bit register              : 1
# Tristates                        : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 1
#      23-bit adder                : 1

Cell Usage :
# BELS                             : 88
#      GND                         : 1
#      LUT1                        : 4
#      LUT1_D                      : 1
#      LUT1_L                      : 21
#      LUT2                        : 3
#      LUT2_D                      : 1
#      LUT3                        : 1
#      LUT3_D                      : 1
#      LUT3_L                      : 1
#      LUT4                        : 6
#      LUT4_D                      : 1
#      LUT4_L                      : 2
#      MUXCY                       : 22
#      VCC                         : 1
#      XORCY                       : 22
# FlipFlops/Latches                : 41
#      FD                          : 1
#      FDC                         : 32
#      FDP                         : 1
#      FDS                         : 7
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 21
#      IBUF                        : 2
#      IOBUF                       : 8
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      25  out of    256     9%  
 Number of Slice Flip Flops:            41  out of    512     8%  
 Number of 4 input LUTs:                42  out of    512     8%  
 Number of bonded IOBs:                 21  out of     88    23%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
SCLK                               | BUFGP                  | 41    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.980ns (Maximum Frequency: 251.256MHz)
   Minimum input arrival time before clock: 2.904ns
   Maximum output required time after clock: 6.072ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'SCLK'
Delay:               3.980ns (Levels of Logic = 24)
  Source:            Indic_Q_0 (FF)
  Destination:       Indic_Q_22 (FF)
  Source Clock:      SCLK rising
  Destination Clock: SCLK rising

  Data Path: Indic_Q_0 to Indic_Q_22
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.494   0.450  Indic_Q_0 (Indic_Q_0)
     LUT1_D:I0->LO         1   0.382   0.000  Indic_Q_LPM_COUNTER_1__n0000<0>lut (N4562)
     MUXCY:S->O            1   0.259   0.000  Indic_Q_LPM_COUNTER_1__n0000<0>cy (Indic_Q_LPM_COUNTER_1__n0000<0>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<1>cy (Indic_Q_LPM_COUNTER_1__n0000<1>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<2>cy (Indic_Q_LPM_COUNTER_1__n0000<2>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<3>cy (Indic_Q_LPM_COUNTER_1__n0000<3>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<4>cy (Indic_Q_LPM_COUNTER_1__n0000<4>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<5>cy (Indic_Q_LPM_COUNTER_1__n0000<5>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<6>cy (Indic_Q_LPM_COUNTER_1__n0000<6>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<7>cy (Indic_Q_LPM_COUNTER_1__n0000<7>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<8>cy (Indic_Q_LPM_COUNTER_1__n0000<8>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<9>cy (Indic_Q_LPM_COUNTER_1__n0000<9>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<10>cy (Indic_Q_LPM_COUNTER_1__n0000<10>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<11>cy (Indic_Q_LPM_COUNTER_1__n0000<11>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<12>cy (Indic_Q_LPM_COUNTER_1__n0000<12>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<13>cy (Indic_Q_LPM_COUNTER_1__n0000<13>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<14>cy (Indic_Q_LPM_COUNTER_1__n0000<14>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<15>cy (Indic_Q_LPM_COUNTER_1__n0000<15>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<16>cy (Indic_Q_LPM_COUNTER_1__n0000<16>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<17>cy (Indic_Q_LPM_COUNTER_1__n0000<17>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<18>cy (Indic_Q_LPM_COUNTER_1__n0000<18>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<19>cy (Indic_Q_LPM_COUNTER_1__n0000<19>_cyo)
     MUXCY:CI->O           1   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<20>cy (Indic_Q_LPM_COUNTER_1__n0000<20>_cyo)
     MUXCY:CI->O           0   0.046   0.000  Indic_Q_LPM_COUNTER_1__n0000<21>cy (Indic_Q_LPM_COUNTER_1__n0000<21>_cyo)
     XORCY:CI->O           1   1.107   0.000  Indic_Q_LPM_COUNTER_1__n0000<22>_xor (Indic_Q__n0000<22>)
     FDC:D                     0.322          Indic_Q_22
    ----------------------------------------
    Total                      3.980ns (3.530ns logic, 0.450ns route)
                                       (88.7% logic, 11.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'SCLK'
Offset:              2.904ns (Levels of Logic = 3)
  Source:            TESTMODE (PAD)
  Destination:       test_OKforCalc (FF)
  Destination Clock: SCLK rising

  Data Path: TESTMODE to test_OKforCalc
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.718   0.650  TESTMODE_IBUF (TESTMODE_IBUF)
     LUT4:I3->O            1   0.382   0.450  test__n001430 (CHOICE324)
     LUT4:I0->O            1   0.382   0.000  test__n0014551 (N4506)
     FDS:D                     0.322          test_OKforCalc
    ----------------------------------------
    Total                      2.904ns (1.804ns logic, 1.100ns route)
                                       (62.1% logic, 37.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'SCLK'
Offset:              6.072ns (Levels of Logic = 2)
  Source:            test_A_0 (FF)
  Destination:       D<0> (PAD)
  Source Clock:      SCLK rising

  Data Path: test_A_0 to D<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              3   0.494   0.630  test_A_0 (test_A_0)
     LUT1:I0->O            8   0.382   0.730  device_or2_D_OUT1 (device_OR2_OUT)
     IOBUF:T->IO               3.836          D_0_IOBUF (D<0>)
    ----------------------------------------
    Total                      6.072ns (4.712ns logic, 1.360ns route)
                                       (77.6% logic, 22.4% route)

=========================================================================
CPU : 13.31 / 14.91 s | Elapsed : 13.00 / 14.00 s
 
--> 

Total memory usage is 66188 kilobytes