project.twr

VHDL source code for test machine.

--------------------------------------------------------------------------------
Release 6.3.03i Trace G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml project project.ncd -o
project.twr project.pcf


Design file:              project.ncd
Physical constraint file: project.pcf
Device,speed:             xc2v40,-5 (PRODUCTION 1.120 2004-11-02, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock SCLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
SDATA       |    1.746(R)|   -0.537(R)|SCLK_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock SCLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
IRQ         |    7.790(R)|SCLK_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock SCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SCLK           |    2.192|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
A<0>           |D<0>           |    6.653|
A<0>           |D<1>           |    6.654|
A<0>           |D<2>           |    6.654|
A<0>           |D<3>           |    5.621|
A<0>           |D<4>           |    6.653|
A<0>           |D<5>           |    5.878|
A<0>           |D<6>           |    6.407|
A<0>           |D<7>           |    6.396|
A<1>           |D<0>           |    6.880|
A<1>           |D<1>           |    6.881|
A<1>           |D<2>           |    6.881|
A<1>           |D<3>           |    5.848|
A<1>           |D<4>           |    6.880|
A<1>           |D<5>           |    6.105|
A<1>           |D<6>           |    6.634|
A<1>           |D<7>           |    6.623|
RD             |D<0>           |    7.361|
RD             |D<1>           |    7.362|
RD             |D<2>           |    7.362|
RD             |D<3>           |    6.329|
RD             |D<4>           |    7.361|
RD             |D<5>           |    6.586|
RD             |D<6>           |    7.115|
RD             |D<7>           |    7.104|
---------------+---------------+---------+

Analysis completed Tue Jun 26 13:03:42 2007
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Peak Memory Usage: 46 MB