testmachine.syr

VHDL source code for test machine.

Release 6.3.03i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.76 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.76 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: testmachine.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : testmachine.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : testmachine
Output Format                      : NGC
Target Device                      : xc2v40-5-fg256

---- Source Options
Top Module Name                    : testmachine
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : testmachine.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/testmachine.vhd in Library work.
Architecture structural of Entity testmachine is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <testmachine> (Architecture <structural>).
INFO:Xst:1304 - Contents of register <SDATA> in unit <testmachine> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <RD> in unit <testmachine> never changes during circuit operation. The register is replaced by logic.
Entity <testmachine> analyzed. Unit <testmachine> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <testmachine>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/testmachine.vhd.
WARNING:Xst:1777 - Inout <REG_OUT> is never used or assigned.
WARNING:Xst:1778 - Inout <RESET> is assigned but never used.
WARNING:Xst:1778 - Inout <A> is assigned but never used.
WARNING:Xst:1779 - Inout <D> is used but is never assigned.
WARNING:Xst:1778 - Inout <RD> is assigned but never used.
WARNING:Xst:1778 - Inout <ResetCalc> is assigned but never used.
WARNING:Xst:1778 - Inout <WR> is assigned but never used.
WARNING:Xst:1778 - Inout <SDATA> is assigned but never used.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 11                                             |
    | Inputs             | 1                                              |
    | Outputs            | 14                                             |
    | Clock              | SCLK (rising_edge)                             |
    | Reset              | START (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <INDSTATE>.
    Found 2-bit register for signal <A>.
    Found 1-bit register for signal <RESET>.
    Found 1-bit register for signal <WR>.
    Found 1-bit register for signal <OKforCalc>.
    Found 1-bit register for signal <OKforReset>.
    Found 1-bit register for signal <ResetIndy>.
    Found 1-bit register for signal <ResetCalc>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  12 D-type flip-flop(s).
Unit <testmachine> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 18
 2-bit register                    : 1
 1-bit register                    : 16
 4-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <A_1> (without init value) is constant in block <testmachine>.

Optimizing unit <testmachine> ...
Loading device for application Xst from file '2v40.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block testmachine, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : testmachine.ngr
Top Level Output File Name         : testmachine
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 33

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 6
#      2-bit register              : 1
#      4-bit register              : 1

Cell Usage :
# BELS                             : 22
#      GND                         : 1
#      LUT1                        : 1
#      LUT2                        : 3
#      LUT2_D                      : 1
#      LUT3                        : 4
#      LUT3_D                      : 1
#      LUT3_L                      : 1
#      LUT4                        : 2
#      LUT4_D                      : 1
#      LUT4_L                      : 7
# FlipFlops/Latches                : 21
#      FD                          : 1
#      FDC                         : 9
#      FDP                         : 1
#      FDS                         : 10
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 24
#      IBUF                        : 10
#      OBUF                        : 14
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      13  out of    256     5%  
 Number of Slice Flip Flops:            21  out of    512     4%  
 Number of 4 input LUTs:                21  out of    512     4%  
 Number of bonded IOBs:                 24  out of     88    27%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
SCLK                               | BUFGP                  | 21    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.940ns (Maximum Frequency: 340.136MHz)
   Minimum input arrival time before clock: 4.108ns
   Maximum output required time after clock: 5.000ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'SCLK'
Delay:               2.940ns (Levels of Logic = 2)
  Source:            state_FFd2 (FF)
  Destination:       A_0 (FF)
  Source Clock:      SCLK rising
  Destination Clock: SCLK rising

  Data Path: state_FFd2 to A_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.494   0.650  state_FFd2 (state_FFd2)
     LUT4_D:I1->O          7   0.382   0.710  state_Out121 (_n0012<1>)
     LUT4_L:I2->LO         1   0.382   0.000  _n0014641 (N3061)
     FDS:D                     0.322          OKforCalc
    ----------------------------------------
    Total                      2.940ns (1.580ns logic, 1.360ns route)
                                       (53.7% logic, 46.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'SCLK'
Offset:              4.108ns (Levels of Logic = 4)
  Source:            TESTMODE (PAD)
  Destination:       OKforCalc (FF)
  Destination Clock: SCLK rising

  Data Path: TESTMODE to OKforCalc
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.718   0.650  TESTMODE_IBUF (TESTMODE_IBUF)
     LUT3:I2->O            1   0.382   0.450  _n001427 (CHOICE323)
     LUT3:I2->O            1   0.382   0.450  _n001430 (CHOICE324)
     LUT3:I2->O            1   0.382   0.450  _n001449 (CHOICE326)
     FDS:S                     0.244          OKforCalc
    ----------------------------------------
    Total                      4.108ns (2.108ns logic, 2.000ns route)
                                       (51.3% logic, 48.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'SCLK'
Offset:              5.000ns (Levels of Logic = 1)
  Source:            RESET (FF)
  Destination:       RESET (PAD)
  Source Clock:      SCLK rising

  Data Path: RESET to RESET
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              2   0.494   0.610  RESET (RESET_OBUF)
     OBUF:I->O                 3.896          RESET_OBUF (RESET)
    ----------------------------------------
    Total                      5.000ns (4.390ns logic, 0.610ns route)
                                       (87.8% logic, 12.2% route)

=========================================================================
CPU : 13.42 / 14.95 s | Elapsed : 14.00 / 15.00 s
 
--> 

Total memory usage is 63116 kilobytes