opit2.ant

VHDL source code for test machine.

-- D:\CSHT\FINAL15.06.07\PROJECT\IMPORTANTVERSION
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Jun 26 13:28:54 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY opit2 IS
END opit2;

ARCHITECTURE testbench_arch OF opit2 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\csht\final15.06.07\project\importantversion\opit2.ano";
	COMPONENT fsm
		PORT (
			SCLK : In  std_logic;
			TESTMODE : In  std_logic;
			START : In  std_logic;
			INDSTATE : Out  std_logic_vector (3 DOWNTO 0);
			OKforCalc : Out  std_logic;
			OKforReset : Out  std_logic;
			Indy : Out  std_logic;
			nIndy : Out  std_logic;
			SDATA : InOut  std_logic;
			A : InOut  std_logic_vector (1 DOWNTO 0);
			D : InOut  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL SCLK : std_logic;
	SIGNAL TESTMODE : std_logic;
	SIGNAL START : std_logic;
	SIGNAL INDSTATE : std_logic_vector (3 DOWNTO 0);
	SIGNAL OKforCalc : std_logic;
	SIGNAL OKforReset : std_logic;
	SIGNAL Indy : std_logic;
	SIGNAL nIndy : std_logic;
	SIGNAL SDATA : std_logic;
	SIGNAL A : std_logic_vector (1 DOWNTO 0);
	SIGNAL D : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : fsm
	PORT MAP (
		SCLK => SCLK,
		TESTMODE => TESTMODE,
		START => START,
		INDSTATE => INDSTATE,
		OKforCalc => OKforCalc,
		OKforReset => OKforReset,
		Indy => Indy,
		nIndy => nIndy,
		SDATA => SDATA,
		A => A,
		D => D
	);

	PROCESS -- clock process for SCLK,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_INDSTATE(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",INDSTATE,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, INDSTATE);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_OKforCalc(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",OKforCalc,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, OKforCalc);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_OKforReset(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",OKforReset,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, OKforReset);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_Indy(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Indy,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Indy);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nIndy(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nIndy,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nIndy);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_SDATA(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",SDATA,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, SDATA);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_A(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",A,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, A);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_D(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",D,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		SCLK <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		SCLK <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_INDSTATE(TX_TIME);
		ANNOTATE_OKforCalc(TX_TIME);
		ANNOTATE_OKforReset(TX_TIME);
		ANNOTATE_Indy(TX_TIME);
		ANNOTATE_nIndy(TX_TIME);
		ANNOTATE_SDATA(TX_TIME);
		ANNOTATE_A(TX_TIME);
		ANNOTATE_D(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		SCLK <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for SCLK
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		TESTMODE <= transport '1';
		START <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		TESTMODE <= transport '0';
		START <= transport '1';
		-- --------------------
		WAIT FOR 110 ns; -- Time=210 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION fsm_cfg OF opit2 IS
	FOR testbench_arch
	END FOR;
END fsm_cfg;