📄 test_machine1.ant

📁 VHDL source code for test machine.
💻 ANT
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-- D:\CSHT\FINAL15.06.07\PROJECT\IMPORTANTVERSION
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Jun 26 13:06:25 2007

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_machine1 IS
END test_machine1;

ARCHITECTURE testbench_arch OF test_machine1 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\csht\final15.06.07\project\importantversion\test_machine1.ano";
	COMPONENT testmachine
		PORT (
			SCLK : In  std_logic;
			START : In  std_logic;
			TESTMODE : In  std_logic;
			INDSTATE : Out  std_logic_vector (3 DOWNTO 0);
			D : InOut  std_logic_vector (7 DOWNTO 0);
			REG_OUT : InOut  std_logic_vector (7 DOWNTO 0);
			SDATA : InOut  std_logic;
			A : InOut  std_logic_vector (1 DOWNTO 0);
			RESET : InOut  std_logic;
			WR : InOut  std_logic;
			RD : InOut  std_logic;
			OKforCalc : Out  std_logic;
			OKforReset : Out  std_logic;
			ResetIndy : Out  std_logic;
			ResetCalc : InOut  std_logic
		);
	END COMPONENT;

	SIGNAL SCLK : std_logic;
	SIGNAL START : std_logic;
	SIGNAL TESTMODE : std_logic;
	SIGNAL INDSTATE : std_logic_vector (3 DOWNTO 0);
	SIGNAL D : std_logic_vector (7 DOWNTO 0);
	SIGNAL REG_OUT : std_logic_vector (7 DOWNTO 0);
	SIGNAL SDATA : std_logic;
	SIGNAL A : std_logic_vector (1 DOWNTO 0);
	SIGNAL RESET : std_logic;
	SIGNAL WR : std_logic;
	SIGNAL RD : std_logic;
	SIGNAL OKforCalc : std_logic;
	SIGNAL OKforReset : std_logic;
	SIGNAL ResetIndy : std_logic;
	SIGNAL ResetCalc : std_logic;

BEGIN
	UUT : testmachine
	PORT MAP (
		SCLK => SCLK,
		START => START,
		TESTMODE => TESTMODE,
		INDSTATE => INDSTATE,
		D => D,
		REG_OUT => REG_OUT,
		SDATA => SDATA,
		A => A,
		RESET => RESET,
		WR => WR,
		RD => RD,
		OKforCalc => OKforCalc,
		OKforReset => OKforReset,
		ResetIndy => ResetIndy,
		ResetCalc => ResetCalc
	);

	PROCESS -- clock process for SCLK,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_INDSTATE(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",INDSTATE,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, INDSTATE);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_OKforCalc(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",OKforCalc,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, OKforCalc);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_OKforReset(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",OKforReset,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, OKforReset);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ResetIndy(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ResetIndy,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ResetIndy);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_D(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",D,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_REG_OUT(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",REG_OUT,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, REG_OUT);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_SDATA(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",SDATA,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, SDATA);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_A(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",A,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, A);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_RESET(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",RESET,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RESET);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_WR(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",WR,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, WR);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_RD(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",RD,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RD);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ResetCalc(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ResetCalc,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ResetCalc);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		SCLK <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		SCLK <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_INDSTATE(TX_TIME);
		ANNOTATE_OKforCalc(TX_TIME);
		ANNOTATE_OKforReset(TX_TIME);
		ANNOTATE_ResetIndy(TX_TIME);
		ANNOTATE_D(TX_TIME);
		ANNOTATE_REG_OUT(TX_TIME);
		ANNOTATE_SDATA(TX_TIME);
		ANNOTATE_A(TX_TIME);
		ANNOTATE_RESET(TX_TIME);
		ANNOTATE_WR(TX_TIME);
		ANNOTATE_RD(TX_TIME);
		ANNOTATE_ResetCalc(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		SCLK <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for SCLK
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		START <= transport '0';
		TESTMODE <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		START <= transport '1';
		-- --------------------
		WAIT FOR 110 ns; -- Time=210 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION testmachine_cfg OF test_machine1 IS
	FOR testbench_arch
	END FOR;
END testmachine_cfg;
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