testproject.ant

VHDL source code for test machine.

-- D:\CSHT\FINAL15.06.07\PROJECT\IMPORTANTVERSION
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Jun 26 13:13:34 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testProject IS
END testProject;

ARCHITECTURE testbench_arch OF testProject IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\csht\final15.06.07\project\importantversion\testProject.ano";
	COMPONENT project
		PORT (
			A : In  std_logic_vector (1 DOWNTO 0);
			SDATA : In  std_logic;
			SCLK : In  std_logic;
			RESET : In  std_logic;
			WR : In  std_logic;
			RD : In  std_logic;
			D : Out  std_logic_vector (7 DOWNTO 0);
			REG_OUT : InOut  std_logic_vector (7 DOWNTO 0);
			IRQ : Out  std_logic
		);
	END COMPONENT;

	SIGNAL A : std_logic_vector (1 DOWNTO 0);
	SIGNAL SDATA : std_logic;
	SIGNAL SCLK : std_logic;
	SIGNAL RESET : std_logic;
	SIGNAL WR : std_logic;
	SIGNAL RD : std_logic;
	SIGNAL D : std_logic_vector (7 DOWNTO 0);
	SIGNAL REG_OUT : std_logic_vector (7 DOWNTO 0);
	SIGNAL IRQ : std_logic;

BEGIN
	UUT : project
	PORT MAP (
		A => A,
		SDATA => SDATA,
		SCLK => SCLK,
		RESET => RESET,
		WR => WR,
		RD => RD,
		D => D,
		REG_OUT => REG_OUT,
		IRQ => IRQ
	);

	PROCESS -- clock process for SCLK,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_D(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",D,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_IRQ(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",IRQ,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, IRQ);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_REG_OUT(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",REG_OUT,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, REG_OUT);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		SCLK <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		SCLK <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_D(TX_TIME);
		ANNOTATE_IRQ(TX_TIME);
		ANNOTATE_REG_OUT(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		SCLK <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for SCLK
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		A <= transport std_logic_vector'("00"); --0
		SDATA <= transport '0';
		RESET <= transport '0';
		WR <= transport '0';
		RD <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		RESET <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		SDATA <= transport '1';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		SDATA <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=500 ns
		SDATA <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		A <= transport std_logic_vector'("01"); --1
		SDATA <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		A <= transport std_logic_vector'("01"); --1
		SDATA <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		A <= transport std_logic_vector'("01"); --1
		SDATA <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		A <= transport std_logic_vector'("01"); --1
		SDATA <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		A <= transport std_logic_vector'("01"); --1
		SDATA <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		A <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 110 ns; -- Time=2110 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION project_cfg OF testProject IS
	FOR testbench_arch
	END FOR;
END project_cfg;