test_machine1.tdo

来自「VHDL source code for test machine.」· TDO 代码 · 共 16 行

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module testmachine
vcom -87 -explicit  testmachine_timesim.vhd
vcom -93 -explicit  test_machine1.timesim_vhw
vsim -t 1ps -sdfmax /UUT=testmachine_timesim.sdf  -lib work test_machine1
do test_machine1.udo
view wave
add wave *
view structure
view signals
run -all
## End