fsm_timesim.vhd

VHDL source code for test machine.

      O => Indic_Q_14_SRFFMUX
    );
  Indic_Q_14_CLKINV_115 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_14_CLKINV
    );
  Indic_Q_16_LOGIC_ZERO_116 : X_ZERO
    port map (
      O => Indic_Q_16_LOGIC_ZERO
    );
  Indic_Q_16_DXMUX_117 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(16),
      O => Indic_Q_16_DXMUX
    );
  Indic_Q_16_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_16_XORF,
      O => Indic_Q_n0000(16)
    );
  Indic_Q_16_XORF_118 : X_XOR2
    port map (
      I0 => Indic_Q_16_CYINIT,
      I1 => Indic_Q_16_F,
      O => Indic_Q_16_XORF
    );
  Indic_Q_16_CYMUXF2_119 : X_MUX2
    port map (
      IA => Indic_Q_16_LOGIC_ZERO,
      IB => Indic_Q_16_LOGIC_ZERO,
      SEL => Indic_Q_16_CYSELF,
      O => Indic_Q_16_CYMUXF2
    );
  Indic_Q_16_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_16_LOGIC_ZERO,
      IB => Indic_Q_16_CYINIT,
      SEL => Indic_Q_16_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_16_cyo
    );
  Indic_Q_16_CYINIT_120 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_15_cyo,
      O => Indic_Q_16_CYINIT
    );
  Indic_Q_16_CYSELF_121 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_16_F,
      O => Indic_Q_16_CYSELF
    );
  Indic_Q_16_DYMUX_122 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(17),
      O => Indic_Q_16_DYMUX
    );
  Indic_Q_16_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_16_XORG,
      O => Indic_Q_n0000(17)
    );
  Indic_Q_16_XORG_123 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_16_cyo,
      I1 => Indic_Q_16_G,
      O => Indic_Q_16_XORG
    );
  Indic_Q_16_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_16_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_17_cyo
    );
  Indic_Q_16_FASTCARRY_124 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_15_cyo,
      O => Indic_Q_16_FASTCARRY
    );
  Indic_Q_16_CYAND_125 : X_AND2
    port map (
      I0 => Indic_Q_16_CYSELG,
      I1 => Indic_Q_16_CYSELF,
      O => Indic_Q_16_CYAND
    );
  Indic_Q_16_CYMUXFAST_126 : X_MUX2
    port map (
      IA => Indic_Q_16_CYMUXG2,
      IB => Indic_Q_16_FASTCARRY,
      SEL => Indic_Q_16_CYAND,
      O => Indic_Q_16_CYMUXFAST
    );
  Indic_Q_16_CYMUXG2_127 : X_MUX2
    port map (
      IA => Indic_Q_16_LOGIC_ZERO,
      IB => Indic_Q_16_CYMUXF2,
      SEL => Indic_Q_16_CYSELG,
      O => Indic_Q_16_CYMUXG2
    );
  Indic_Q_16_CYSELG_128 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_16_G,
      O => Indic_Q_16_CYSELG
    );
  Indic_Q_16_SRFFMUX_129 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_16_SRFFMUX
    );
  Indic_Q_16_CLKINV_130 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_16_CLKINV
    );
  Indic_Q_18_LOGIC_ZERO_131 : X_ZERO
    port map (
      O => Indic_Q_18_LOGIC_ZERO
    );
  Indic_Q_18_DXMUX_132 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(18),
      O => Indic_Q_18_DXMUX
    );
  Indic_Q_18_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_18_XORF,
      O => Indic_Q_n0000(18)
    );
  Indic_Q_18_XORF_133 : X_XOR2
    port map (
      I0 => Indic_Q_18_CYINIT,
      I1 => Indic_Q_18_F,
      O => Indic_Q_18_XORF
    );
  Indic_Q_18_CYMUXF2_134 : X_MUX2
    port map (
      IA => Indic_Q_18_LOGIC_ZERO,
      IB => Indic_Q_18_LOGIC_ZERO,
      SEL => Indic_Q_18_CYSELF,
      O => Indic_Q_18_CYMUXF2
    );
  Indic_Q_18_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_18_LOGIC_ZERO,
      IB => Indic_Q_18_CYINIT,
      SEL => Indic_Q_18_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_18_cyo
    );
  Indic_Q_18_CYINIT_135 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_17_cyo,
      O => Indic_Q_18_CYINIT
    );
  Indic_Q_18_CYSELF_136 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_18_F,
      O => Indic_Q_18_CYSELF
    );
  Indic_Q_18_DYMUX_137 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(19),
      O => Indic_Q_18_DYMUX
    );
  Indic_Q_18_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_18_XORG,
      O => Indic_Q_n0000(19)
    );
  Indic_Q_18_XORG_138 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_18_cyo,
      I1 => Indic_Q_18_G,
      O => Indic_Q_18_XORG
    );
  Indic_Q_18_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_18_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_19_cyo
    );
  Indic_Q_18_FASTCARRY_139 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_17_cyo,
      O => Indic_Q_18_FASTCARRY
    );
  Indic_Q_18_CYAND_140 : X_AND2
    port map (
      I0 => Indic_Q_18_CYSELG,
      I1 => Indic_Q_18_CYSELF,
      O => Indic_Q_18_CYAND
    );
  Indic_Q_18_CYMUXFAST_141 : X_MUX2
    port map (
      IA => Indic_Q_18_CYMUXG2,
      IB => Indic_Q_18_FASTCARRY,
      SEL => Indic_Q_18_CYAND,
      O => Indic_Q_18_CYMUXFAST
    );
  Indic_Q_18_CYMUXG2_142 : X_MUX2
    port map (
      IA => Indic_Q_18_LOGIC_ZERO,
      IB => Indic_Q_18_CYMUXF2,
      SEL => Indic_Q_18_CYSELG,
      O => Indic_Q_18_CYMUXG2
    );
  Indic_Q_18_CYSELG_143 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_18_G,
      O => Indic_Q_18_CYSELG
    );
  Indic_Q_18_SRFFMUX_144 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_18_SRFFMUX
    );
  Indic_Q_18_CLKINV_145 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_18_CLKINV
    );
  Indic_Q_20_LOGIC_ZERO_146 : X_ZERO
    port map (
      O => Indic_Q_20_LOGIC_ZERO
    );
  Indic_Q_20_DXMUX_147 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(20),
      O => Indic_Q_20_DXMUX
    );
  Indic_Q_20_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_20_XORF,
      O => Indic_Q_n0000(20)
    );
  Indic_Q_20_XORF_148 : X_XOR2
    port map (
      I0 => Indic_Q_20_CYINIT,
      I1 => Indic_Q_20_F,
      O => Indic_Q_20_XORF
    );
  Indic_Q_20_CYMUXF2_149 : X_MUX2
    port map (
      IA => Indic_Q_20_LOGIC_ZERO,
      IB => Indic_Q_20_LOGIC_ZERO,
      SEL => Indic_Q_20_CYSELF,
      O => Indic_Q_20_CYMUXF2
    );
  Indic_Q_20_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_20_LOGIC_ZERO,
      IB => Indic_Q_20_CYINIT,
      SEL => Indic_Q_20_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_20_cyo
    );
  Indic_Q_20_CYINIT_150 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_19_cyo,
      O => Indic_Q_20_CYINIT
    );
  Indic_Q_20_CYSELF_151 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_20_F,
      O => Indic_Q_20_CYSELF
    );
  Indic_Q_20_DYMUX_152 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(21),
      O => Indic_Q_20_DYMUX
    );
  Indic_Q_20_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_20_XORG,
      O => Indic_Q_n0000(21)
    );
  Indic_Q_20_XORG_153 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_20_cyo,
      I1 => Indic_Q_20_G,
      O => Indic_Q_20_XORG
    );
  Indic_Q_20_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_20_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_21_cyo
    );
  Indic_Q_20_FASTCARRY_154 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_19_cyo,
      O => Indic_Q_20_FASTCARRY
    );
  Indic_Q_20_CYAND_155 : X_AND2
    port map (
      I0 => Indic_Q_20_CYSELG,
      I1 => Indic_Q_20_CYSELF,
      O => Indic_Q_20_CYAND
    );
  Indic_Q_20_CYMUXFAST_156 : X_MUX2
    port map (
      IA => Indic_Q_20_CYMUXG2,
      IB => Indic_Q_20_FASTCARRY,
      SEL => Indic_Q_20_CYAND,
      O => Indic_Q_20_CYMUXFAST
    );
  Indic_Q_20_CYMUXG2_157 : X_MUX2
    port map (
      IA => Indic_Q_20_LOGIC_ZERO,
      IB => Indic_Q_20_CYMUXF2,
      SEL => Indic_Q_20_CYSELG,
      O => Indic_Q_20_CYMUXG2
    );
  Indic_Q_20_CYSELG_158 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_20_G,
      O => Indic_Q_20_CYSELG
    );
  Indic_Q_20_SRFFMUX_159 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_20_SRFFMUX
    );
  Indic_Q_20_CLKINV_160 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_20_CLKINV
    );
  Indic_Q_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Indic_Q_0_DYMUX,
      CE => VCC,
      CLK => Indic_Q_0_CLKINV,
      SET => GND,
      RST => Indic_Q_0_FFY_RST,
      O => Indic_Q(1)
    );
  Indic_Q_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Indic_Q_0_SRFFMUX,
      I1 => GSR,
      O => Indic_Q_0_FFY_RST
    );
  Indic_Q_22_DXMUX_161 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(22),
      O => Indic_Q_22_DXMUX
    );
  Indic_Q_22_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_22_XORF,
      O => Indic_Q_n0000(22)
    );
  Indic_Q_22_XORF_162 : X_XOR2
    port map (
      I0 => Indic_Q_22_CYINIT,
      I1 => Indic_Q_22_rt,
      O => Indic_Q_22_XORF
    );
  Indic_Q_22_CYINIT_163 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_21_cyo,
      O => Indic_Q_22_CYINIT
    );
  Indic_Q_22_CLKINV_164 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_22_CLKINV
    );
  TESTMODE_IBUF_165 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => TESTMODE,
      O => TESTMODE_INBUF
    );
  A_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_0_O,
      CTL => A_0_ENABLE,
      O => A(0)
    );
  A_0_ENABLEINV : X_INV
    port map (
      I => A_0_GTS_OR_T,
      O => A_0_ENABLE
    );
  A_0_GTS_OR_T_166 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => A_0_GTS_OR_T
    );
  A_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_1_O,
      CTL => A_1_ENABLE,
      O => A(1)
    );
  A_1_ENABLEINV : X_INV
    port map (
      I => A_1_GTS_OR_T,
      O => A_1_ENABLE
    );
  A_1_GTS_OR_T_167 : X_BUF_PP
    generic map(