fsm_timesim.vhd

VHDL source code for test machine.

    port map (
      I => Indic_Q_8_XORF,
      O => Indic_Q_n0000(8)
    );
  Indic_Q_8_XORF_58 : X_XOR2
    port map (
      I0 => Indic_Q_8_CYINIT,
      I1 => Indic_Q_8_F,
      O => Indic_Q_8_XORF
    );
  Indic_Q_8_CYMUXF2_59 : X_MUX2
    port map (
      IA => Indic_Q_8_LOGIC_ZERO,
      IB => Indic_Q_8_LOGIC_ZERO,
      SEL => Indic_Q_8_CYSELF,
      O => Indic_Q_8_CYMUXF2
    );
  Indic_Q_8_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_8_LOGIC_ZERO,
      IB => Indic_Q_8_CYINIT,
      SEL => Indic_Q_8_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_8_cyo
    );
  Indic_Q_8_CYINIT_60 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_7_cyo,
      O => Indic_Q_8_CYINIT
    );
  Indic_Q_8_CYSELF_61 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_8_F,
      O => Indic_Q_8_CYSELF
    );
  Indic_Q_8_DYMUX_62 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(9),
      O => Indic_Q_8_DYMUX
    );
  Indic_Q_8_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_8_XORG,
      O => Indic_Q_n0000(9)
    );
  Indic_Q_8_XORG_63 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_8_cyo,
      I1 => Indic_Q_8_G,
      O => Indic_Q_8_XORG
    );
  Indic_Q_8_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_8_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_9_cyo
    );
  Indic_Q_8_FASTCARRY_64 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_7_cyo,
      O => Indic_Q_8_FASTCARRY
    );
  Indic_Q_8_CYAND_65 : X_AND2
    port map (
      I0 => Indic_Q_8_CYSELG,
      I1 => Indic_Q_8_CYSELF,
      O => Indic_Q_8_CYAND
    );
  Indic_Q_8_CYMUXFAST_66 : X_MUX2
    port map (
      IA => Indic_Q_8_CYMUXG2,
      IB => Indic_Q_8_FASTCARRY,
      SEL => Indic_Q_8_CYAND,
      O => Indic_Q_8_CYMUXFAST
    );
  Indic_Q_8_CYMUXG2_67 : X_MUX2
    port map (
      IA => Indic_Q_8_LOGIC_ZERO,
      IB => Indic_Q_8_CYMUXF2,
      SEL => Indic_Q_8_CYSELG,
      O => Indic_Q_8_CYMUXG2
    );
  Indic_Q_8_CYSELG_68 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_8_G,
      O => Indic_Q_8_CYSELG
    );
  Indic_Q_8_SRFFMUX_69 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_8_SRFFMUX
    );
  Indic_Q_8_CLKINV_70 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_8_CLKINV
    );
  Indic_Q_10_LOGIC_ZERO_71 : X_ZERO
    port map (
      O => Indic_Q_10_LOGIC_ZERO
    );
  Indic_Q_10_DXMUX_72 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(10),
      O => Indic_Q_10_DXMUX
    );
  Indic_Q_10_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_10_XORF,
      O => Indic_Q_n0000(10)
    );
  Indic_Q_10_XORF_73 : X_XOR2
    port map (
      I0 => Indic_Q_10_CYINIT,
      I1 => Indic_Q_10_F,
      O => Indic_Q_10_XORF
    );
  Indic_Q_10_CYMUXF2_74 : X_MUX2
    port map (
      IA => Indic_Q_10_LOGIC_ZERO,
      IB => Indic_Q_10_LOGIC_ZERO,
      SEL => Indic_Q_10_CYSELF,
      O => Indic_Q_10_CYMUXF2
    );
  Indic_Q_10_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_10_LOGIC_ZERO,
      IB => Indic_Q_10_CYINIT,
      SEL => Indic_Q_10_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_10_cyo
    );
  Indic_Q_10_CYINIT_75 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_9_cyo,
      O => Indic_Q_10_CYINIT
    );
  Indic_Q_10_CYSELF_76 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_10_F,
      O => Indic_Q_10_CYSELF
    );
  Indic_Q_10_DYMUX_77 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(11),
      O => Indic_Q_10_DYMUX
    );
  Indic_Q_10_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_10_XORG,
      O => Indic_Q_n0000(11)
    );
  Indic_Q_10_XORG_78 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_10_cyo,
      I1 => Indic_Q_10_G,
      O => Indic_Q_10_XORG
    );
  Indic_Q_10_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_10_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_11_cyo
    );
  Indic_Q_10_FASTCARRY_79 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_9_cyo,
      O => Indic_Q_10_FASTCARRY
    );
  Indic_Q_10_CYAND_80 : X_AND2
    port map (
      I0 => Indic_Q_10_CYSELG,
      I1 => Indic_Q_10_CYSELF,
      O => Indic_Q_10_CYAND
    );
  Indic_Q_10_CYMUXFAST_81 : X_MUX2
    port map (
      IA => Indic_Q_10_CYMUXG2,
      IB => Indic_Q_10_FASTCARRY,
      SEL => Indic_Q_10_CYAND,
      O => Indic_Q_10_CYMUXFAST
    );
  Indic_Q_10_CYMUXG2_82 : X_MUX2
    port map (
      IA => Indic_Q_10_LOGIC_ZERO,
      IB => Indic_Q_10_CYMUXF2,
      SEL => Indic_Q_10_CYSELG,
      O => Indic_Q_10_CYMUXG2
    );
  Indic_Q_10_CYSELG_83 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_10_G,
      O => Indic_Q_10_CYSELG
    );
  Indic_Q_10_SRFFMUX_84 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_10_SRFFMUX
    );
  Indic_Q_10_CLKINV_85 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_10_CLKINV
    );
  Indic_Q_12_LOGIC_ZERO_86 : X_ZERO
    port map (
      O => Indic_Q_12_LOGIC_ZERO
    );
  Indic_Q_12_DXMUX_87 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(12),
      O => Indic_Q_12_DXMUX
    );
  Indic_Q_12_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_12_XORF,
      O => Indic_Q_n0000(12)
    );
  Indic_Q_12_XORF_88 : X_XOR2
    port map (
      I0 => Indic_Q_12_CYINIT,
      I1 => Indic_Q_12_F,
      O => Indic_Q_12_XORF
    );
  Indic_Q_12_CYMUXF2_89 : X_MUX2
    port map (
      IA => Indic_Q_12_LOGIC_ZERO,
      IB => Indic_Q_12_LOGIC_ZERO,
      SEL => Indic_Q_12_CYSELF,
      O => Indic_Q_12_CYMUXF2
    );
  Indic_Q_12_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_12_LOGIC_ZERO,
      IB => Indic_Q_12_CYINIT,
      SEL => Indic_Q_12_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_12_cyo
    );
  Indic_Q_12_CYINIT_90 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_11_cyo,
      O => Indic_Q_12_CYINIT
    );
  Indic_Q_12_CYSELF_91 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_12_F,
      O => Indic_Q_12_CYSELF
    );
  Indic_Q_12_DYMUX_92 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(13),
      O => Indic_Q_12_DYMUX
    );
  Indic_Q_12_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_12_XORG,
      O => Indic_Q_n0000(13)
    );
  Indic_Q_12_XORG_93 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_12_cyo,
      I1 => Indic_Q_12_G,
      O => Indic_Q_12_XORG
    );
  Indic_Q_12_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_12_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_13_cyo
    );
  Indic_Q_12_FASTCARRY_94 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_11_cyo,
      O => Indic_Q_12_FASTCARRY
    );
  Indic_Q_12_CYAND_95 : X_AND2
    port map (
      I0 => Indic_Q_12_CYSELG,
      I1 => Indic_Q_12_CYSELF,
      O => Indic_Q_12_CYAND
    );
  Indic_Q_12_CYMUXFAST_96 : X_MUX2
    port map (
      IA => Indic_Q_12_CYMUXG2,
      IB => Indic_Q_12_FASTCARRY,
      SEL => Indic_Q_12_CYAND,
      O => Indic_Q_12_CYMUXFAST
    );
  Indic_Q_12_CYMUXG2_97 : X_MUX2
    port map (
      IA => Indic_Q_12_LOGIC_ZERO,
      IB => Indic_Q_12_CYMUXF2,
      SEL => Indic_Q_12_CYSELG,
      O => Indic_Q_12_CYMUXG2
    );
  Indic_Q_12_CYSELG_98 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_12_G,
      O => Indic_Q_12_CYSELG
    );
  Indic_Q_12_SRFFMUX_99 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_12_SRFFMUX
    );
  Indic_Q_12_CLKINV_100 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_12_CLKINV
    );
  Indic_Q_14_LOGIC_ZERO_101 : X_ZERO
    port map (
      O => Indic_Q_14_LOGIC_ZERO
    );
  Indic_Q_14_DXMUX_102 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(14),
      O => Indic_Q_14_DXMUX
    );
  Indic_Q_14_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_14_XORF,
      O => Indic_Q_n0000(14)
    );
  Indic_Q_14_XORF_103 : X_XOR2
    port map (
      I0 => Indic_Q_14_CYINIT,
      I1 => Indic_Q_14_F,
      O => Indic_Q_14_XORF
    );
  Indic_Q_14_CYMUXF2_104 : X_MUX2
    port map (
      IA => Indic_Q_14_LOGIC_ZERO,
      IB => Indic_Q_14_LOGIC_ZERO,
      SEL => Indic_Q_14_CYSELF,
      O => Indic_Q_14_CYMUXF2
    );
  Indic_Q_14_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_14_LOGIC_ZERO,
      IB => Indic_Q_14_CYINIT,
      SEL => Indic_Q_14_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_14_cyo
    );
  Indic_Q_14_CYINIT_105 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_13_cyo,
      O => Indic_Q_14_CYINIT
    );
  Indic_Q_14_CYSELF_106 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_14_F,
      O => Indic_Q_14_CYSELF
    );
  Indic_Q_14_DYMUX_107 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(15),
      O => Indic_Q_14_DYMUX
    );
  Indic_Q_14_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_14_XORG,
      O => Indic_Q_n0000(15)
    );
  Indic_Q_14_XORG_108 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_14_cyo,
      I1 => Indic_Q_14_G,
      O => Indic_Q_14_XORG
    );
  Indic_Q_14_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_14_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_15_cyo
    );
  Indic_Q_14_FASTCARRY_109 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_13_cyo,
      O => Indic_Q_14_FASTCARRY
    );
  Indic_Q_14_CYAND_110 : X_AND2
    port map (
      I0 => Indic_Q_14_CYSELG,
      I1 => Indic_Q_14_CYSELF,
      O => Indic_Q_14_CYAND
    );
  Indic_Q_14_CYMUXFAST_111 : X_MUX2
    port map (
      IA => Indic_Q_14_CYMUXG2,
      IB => Indic_Q_14_FASTCARRY,
      SEL => Indic_Q_14_CYAND,
      O => Indic_Q_14_CYMUXFAST
    );
  Indic_Q_14_CYMUXG2_112 : X_MUX2
    port map (
      IA => Indic_Q_14_LOGIC_ZERO,
      IB => Indic_Q_14_CYMUXF2,
      SEL => Indic_Q_14_CYSELG,
      O => Indic_Q_14_CYMUXG2
    );
  Indic_Q_14_CYSELG_113 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_14_G,
      O => Indic_Q_14_CYSELG
    );
  Indic_Q_14_SRFFMUX_114 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,