fsm_timesim.vhd

VHDL source code for test machine.

    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_0_F,
      O => Indic_Q_N999
    );
  Indic_Q_0_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_0_LOGIC_ONE,
      IB => Indic_Q_0_CYINIT,
      SEL => Indic_Q_0_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_0_cyo
    );
  Indic_Q_0_CYINIT_3 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_0_BXINVNOT,
      O => Indic_Q_0_CYINIT
    );
  Indic_Q_0_CYSELF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_0_F,
      O => Indic_Q_0_CYSELF
    );
  Indic_Q_0_BXINV : X_INV
    port map (
      I => GLOBAL_LOGIC1_3,
      O => Indic_Q_0_BXINVNOT
    );
  Indic_Q_0_DYMUX_5 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(1),
      O => Indic_Q_0_DYMUX
    );
  Indic_Q_0_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_0_XORG,
      O => Indic_Q_n0000(1)
    );
  Indic_Q_0_XORG_6 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_0_cyo,
      I1 => Indic_Q_0_G,
      O => Indic_Q_0_XORG
    );
  Indic_Q_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_0_CYMUXG,
      O => Indic_Q_LPM_COUNTER_1_n0000_1_cyo
    );
  Indic_Q_0_CYMUXG_7 : X_MUX2
    port map (
      IA => Indic_Q_0_LOGIC_ZERO,
      IB => Indic_Q_LPM_COUNTER_1_n0000_0_cyo,
      SEL => Indic_Q_0_CYSELG,
      O => Indic_Q_0_CYMUXG
    );
  Indic_Q_0_CYSELG_8 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_0_G,
      O => Indic_Q_0_CYSELG
    );
  Indic_Q_0_SRFFMUX_9 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_0_SRFFMUX
    );
  Indic_Q_0_CLKINV_10 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_0_CLKINV
    );
  Indic_Q_2_LOGIC_ZERO_11 : X_ZERO
    port map (
      O => Indic_Q_2_LOGIC_ZERO
    );
  Indic_Q_2_DXMUX_12 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(2),
      O => Indic_Q_2_DXMUX
    );
  Indic_Q_2_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_2_XORF,
      O => Indic_Q_n0000(2)
    );
  Indic_Q_2_XORF_13 : X_XOR2
    port map (
      I0 => Indic_Q_2_CYINIT,
      I1 => Indic_Q_2_F,
      O => Indic_Q_2_XORF
    );
  Indic_Q_2_CYMUXF2_14 : X_MUX2
    port map (
      IA => Indic_Q_2_LOGIC_ZERO,
      IB => Indic_Q_2_LOGIC_ZERO,
      SEL => Indic_Q_2_CYSELF,
      O => Indic_Q_2_CYMUXF2
    );
  Indic_Q_2_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_2_LOGIC_ZERO,
      IB => Indic_Q_2_CYINIT,
      SEL => Indic_Q_2_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_2_cyo
    );
  Indic_Q_2_CYINIT_15 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_1_cyo,
      O => Indic_Q_2_CYINIT
    );
  Indic_Q_2_CYSELF_16 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_2_F,
      O => Indic_Q_2_CYSELF
    );
  Indic_Q_2_DYMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(3),
      O => Indic_Q_2_DYMUX
    );
  Indic_Q_2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_2_XORG,
      O => Indic_Q_n0000(3)
    );
  Indic_Q_2_XORG_18 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_2_cyo,
      I1 => Indic_Q_2_G,
      O => Indic_Q_2_XORG
    );
  Indic_Q_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_2_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_3_cyo
    );
  Indic_Q_2_FASTCARRY_19 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_1_cyo,
      O => Indic_Q_2_FASTCARRY
    );
  Indic_Q_2_CYAND_20 : X_AND2
    port map (
      I0 => Indic_Q_2_CYSELG,
      I1 => Indic_Q_2_CYSELF,
      O => Indic_Q_2_CYAND
    );
  Indic_Q_2_CYMUXFAST_21 : X_MUX2
    port map (
      IA => Indic_Q_2_CYMUXG2,
      IB => Indic_Q_2_FASTCARRY,
      SEL => Indic_Q_2_CYAND,
      O => Indic_Q_2_CYMUXFAST
    );
  Indic_Q_2_CYMUXG2_22 : X_MUX2
    port map (
      IA => Indic_Q_2_LOGIC_ZERO,
      IB => Indic_Q_2_CYMUXF2,
      SEL => Indic_Q_2_CYSELG,
      O => Indic_Q_2_CYMUXG2
    );
  Indic_Q_2_CYSELG_23 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_2_G,
      O => Indic_Q_2_CYSELG
    );
  Indic_Q_2_SRFFMUX_24 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_2_SRFFMUX
    );
  Indic_Q_2_CLKINV_25 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_2_CLKINV
    );
  Indic_Q_4_LOGIC_ZERO_26 : X_ZERO
    port map (
      O => Indic_Q_4_LOGIC_ZERO
    );
  Indic_Q_4_DXMUX_27 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(4),
      O => Indic_Q_4_DXMUX
    );
  Indic_Q_4_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_4_XORF,
      O => Indic_Q_n0000(4)
    );
  Indic_Q_4_XORF_28 : X_XOR2
    port map (
      I0 => Indic_Q_4_CYINIT,
      I1 => Indic_Q_4_F,
      O => Indic_Q_4_XORF
    );
  Indic_Q_4_CYMUXF2_29 : X_MUX2
    port map (
      IA => Indic_Q_4_LOGIC_ZERO,
      IB => Indic_Q_4_LOGIC_ZERO,
      SEL => Indic_Q_4_CYSELF,
      O => Indic_Q_4_CYMUXF2
    );
  Indic_Q_4_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_4_LOGIC_ZERO,
      IB => Indic_Q_4_CYINIT,
      SEL => Indic_Q_4_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_4_cyo
    );
  Indic_Q_4_CYINIT_30 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_3_cyo,
      O => Indic_Q_4_CYINIT
    );
  Indic_Q_4_CYSELF_31 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_4_F,
      O => Indic_Q_4_CYSELF
    );
  Indic_Q_4_DYMUX_32 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(5),
      O => Indic_Q_4_DYMUX
    );
  Indic_Q_4_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_4_XORG,
      O => Indic_Q_n0000(5)
    );
  Indic_Q_4_XORG_33 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_4_cyo,
      I1 => Indic_Q_4_G,
      O => Indic_Q_4_XORG
    );
  Indic_Q_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_4_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_5_cyo
    );
  Indic_Q_4_FASTCARRY_34 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_3_cyo,
      O => Indic_Q_4_FASTCARRY
    );
  Indic_Q_4_CYAND_35 : X_AND2
    port map (
      I0 => Indic_Q_4_CYSELG,
      I1 => Indic_Q_4_CYSELF,
      O => Indic_Q_4_CYAND
    );
  Indic_Q_4_CYMUXFAST_36 : X_MUX2
    port map (
      IA => Indic_Q_4_CYMUXG2,
      IB => Indic_Q_4_FASTCARRY,
      SEL => Indic_Q_4_CYAND,
      O => Indic_Q_4_CYMUXFAST
    );
  Indic_Q_4_CYMUXG2_37 : X_MUX2
    port map (
      IA => Indic_Q_4_LOGIC_ZERO,
      IB => Indic_Q_4_CYMUXF2,
      SEL => Indic_Q_4_CYSELG,
      O => Indic_Q_4_CYMUXG2
    );
  Indic_Q_4_CYSELG_38 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_4_G,
      O => Indic_Q_4_CYSELG
    );
  Indic_Q_4_SRFFMUX_39 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_4_SRFFMUX
    );
  Indic_Q_4_CLKINV_40 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_4_CLKINV
    );
  Indic_Q_6_LOGIC_ZERO_41 : X_ZERO
    port map (
      O => Indic_Q_6_LOGIC_ZERO
    );
  Indic_Q_6_DXMUX_42 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(6),
      O => Indic_Q_6_DXMUX
    );
  Indic_Q_6_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_6_XORF,
      O => Indic_Q_n0000(6)
    );
  Indic_Q_6_XORF_43 : X_XOR2
    port map (
      I0 => Indic_Q_6_CYINIT,
      I1 => Indic_Q_6_F,
      O => Indic_Q_6_XORF
    );
  Indic_Q_6_CYMUXF2_44 : X_MUX2
    port map (
      IA => Indic_Q_6_LOGIC_ZERO,
      IB => Indic_Q_6_LOGIC_ZERO,
      SEL => Indic_Q_6_CYSELF,
      O => Indic_Q_6_CYMUXF2
    );
  Indic_Q_6_CYMUXF : X_MUX2
    port map (
      IA => Indic_Q_6_LOGIC_ZERO,
      IB => Indic_Q_6_CYINIT,
      SEL => Indic_Q_6_CYSELF,
      O => Indic_Q_LPM_COUNTER_1_n0000_6_cyo
    );
  Indic_Q_6_CYINIT_45 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_5_cyo,
      O => Indic_Q_6_CYINIT
    );
  Indic_Q_6_CYSELF_46 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_6_F,
      O => Indic_Q_6_CYSELF
    );
  Indic_Q_6_DYMUX_47 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(7),
      O => Indic_Q_6_DYMUX
    );
  Indic_Q_6_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_6_XORG,
      O => Indic_Q_n0000(7)
    );
  Indic_Q_6_XORG_48 : X_XOR2
    port map (
      I0 => Indic_Q_LPM_COUNTER_1_n0000_6_cyo,
      I1 => Indic_Q_6_G,
      O => Indic_Q_6_XORG
    );
  Indic_Q_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_6_CYMUXFAST,
      O => Indic_Q_LPM_COUNTER_1_n0000_7_cyo
    );
  Indic_Q_6_FASTCARRY_49 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_LPM_COUNTER_1_n0000_5_cyo,
      O => Indic_Q_6_FASTCARRY
    );
  Indic_Q_6_CYAND_50 : X_AND2
    port map (
      I0 => Indic_Q_6_CYSELG,
      I1 => Indic_Q_6_CYSELF,
      O => Indic_Q_6_CYAND
    );
  Indic_Q_6_CYMUXFAST_51 : X_MUX2
    port map (
      IA => Indic_Q_6_CYMUXG2,
      IB => Indic_Q_6_FASTCARRY,
      SEL => Indic_Q_6_CYAND,
      O => Indic_Q_6_CYMUXFAST
    );
  Indic_Q_6_CYMUXG2_52 : X_MUX2
    port map (
      IA => Indic_Q_6_LOGIC_ZERO,
      IB => Indic_Q_6_CYMUXF2,
      SEL => Indic_Q_6_CYSELG,
      O => Indic_Q_6_CYMUXG2
    );
  Indic_Q_6_CYSELG_53 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_6_G,
      O => Indic_Q_6_CYSELG
    );
  Indic_Q_6_SRFFMUX_54 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => test_ResetIndy,
      O => Indic_Q_6_SRFFMUX
    );
  Indic_Q_6_CLKINV_55 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => Indic_Q_6_CLKINV
    );
  Indic_Q_8_LOGIC_ZERO_56 : X_ZERO
    port map (
      O => Indic_Q_8_LOGIC_ZERO
    );
  Indic_Q_8_DXMUX_57 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_n0000(8),
      O => Indic_Q_8_DXMUX
    );
  Indic_Q_8_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )