fsm_timesim.vhd

VHDL source code for test machine.

-- Xilinx Vhdl netlist produced by netgen application (version G.38)
-- Command       : -intstyle ise -s 5 -pcf fsm.pcf -ngm fsm.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim fsm.ncd fsm_timesim.vhd 
-- Input file    : fsm.ncd
-- Output file   : fsm_timesim.vhd
-- Design name   : fsm
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2v40fg256-5 (PRODUCTION 1.120 2004-11-02, STEPPING 1)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity fsm is
  port (
    Indy : out STD_LOGIC; 
    OKforCalc : out STD_LOGIC; 
    nIndy : out STD_LOGIC; 
    OKforReset : out STD_LOGIC; 
    SDATA : inout STD_LOGIC; 
    TESTMODE : in STD_LOGIC := 'X'; 
    SCLK : in STD_LOGIC := 'X'; 
    START : in STD_LOGIC := 'X'; 
    INDSTATE : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    D : inout STD_LOGIC_VECTOR ( 7 downto 0 ); 
    A : inout STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end fsm;

architecture Structure of fsm is
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal SCLK_BUFGP : STD_LOGIC; 
  signal test_ResetIndy : STD_LOGIC; 
  signal Indic_Q_N999 : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_5_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_7_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_9_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_11_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_13_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_15_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_17_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_19_cyo : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_21_cyo : STD_LOGIC; 
  signal TESTMODE_IBUF : STD_LOGIC; 
  signal N4469 : STD_LOGIC; 
  signal N4471 : STD_LOGIC; 
  signal N4473 : STD_LOGIC; 
  signal N4476 : STD_LOGIC; 
  signal N4479 : STD_LOGIC; 
  signal test_OKforCalc : STD_LOGIC; 
  signal N4481 : STD_LOGIC; 
  signal N4483 : STD_LOGIC; 
  signal N4485 : STD_LOGIC; 
  signal SCLK_BUFGP_IBUFG : STD_LOGIC; 
  signal test_state_FFd6 : STD_LOGIC; 
  signal N4496 : STD_LOGIC; 
  signal test_state_FFd3 : STD_LOGIC; 
  signal N4509 : STD_LOGIC; 
  signal test_state_FFd1 : STD_LOGIC; 
  signal test_state_FFd4 : STD_LOGIC; 
  signal START_IBUF : STD_LOGIC; 
  signal test_OKforReset : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal test_state_FFd9 : STD_LOGIC; 
  signal test_state_FFd2 : STD_LOGIC; 
  signal test_state_FFd8 : STD_LOGIC; 
  signal test_state_FFd4_In : STD_LOGIC; 
  signal test_n0017_0_11_O : STD_LOGIC; 
  signal CHOICE306 : STD_LOGIC; 
  signal test_N2007 : STD_LOGIC; 
  signal test_n0015_SW181_O : STD_LOGIC; 
  signal test_state_FFd7 : STD_LOGIC; 
  signal CHOICE309 : STD_LOGIC; 
  signal test_state_FFd10 : STD_LOGIC; 
  signal test_state_FFd9_In : STD_LOGIC; 
  signal N4291 : STD_LOGIC; 
  signal test_state_FFd5 : STD_LOGIC; 
  signal test_n00161_O : STD_LOGIC; 
  signal CHOICE324 : STD_LOGIC; 
  signal N4547 : STD_LOGIC; 
  signal N4506 : STD_LOGIC; 
  signal test_state_FFd8_In : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_2 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_3 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_4 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_5 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_6 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Indic_Q_0_DXMUX : STD_LOGIC; 
  signal Indic_Q_0_LOGIC_ONE : STD_LOGIC; 
  signal Indic_Q_0_CYINIT : STD_LOGIC; 
  signal Indic_Q_0_CYSELF : STD_LOGIC; 
  signal Indic_Q_0_F : STD_LOGIC; 
  signal Indic_Q_0_BXINVNOT : STD_LOGIC; 
  signal Indic_Q_0_DYMUX : STD_LOGIC; 
  signal Indic_Q_0_XORG : STD_LOGIC; 
  signal Indic_Q_0_CYMUXG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal Indic_Q_0_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_0_CYSELG : STD_LOGIC; 
  signal Indic_Q_0_G : STD_LOGIC; 
  signal Indic_Q_0_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_0_CLKINV : STD_LOGIC; 
  signal Indic_Q_2_DXMUX : STD_LOGIC; 
  signal Indic_Q_2_XORF : STD_LOGIC; 
  signal Indic_Q_2_CYINIT : STD_LOGIC; 
  signal Indic_Q_2_F : STD_LOGIC; 
  signal Indic_Q_2_DYMUX : STD_LOGIC; 
  signal Indic_Q_2_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal Indic_Q_2_CYSELF : STD_LOGIC; 
  signal Indic_Q_2_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_2_CYAND : STD_LOGIC; 
  signal Indic_Q_2_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_2_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_2_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_2_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_2_CYSELG : STD_LOGIC; 
  signal Indic_Q_2_G : STD_LOGIC; 
  signal Indic_Q_2_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_2_CLKINV : STD_LOGIC; 
  signal Indic_Q_4_DXMUX : STD_LOGIC; 
  signal Indic_Q_4_XORF : STD_LOGIC; 
  signal Indic_Q_4_CYINIT : STD_LOGIC; 
  signal Indic_Q_4_F : STD_LOGIC; 
  signal Indic_Q_4_DYMUX : STD_LOGIC; 
  signal Indic_Q_4_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_4_cyo : STD_LOGIC; 
  signal Indic_Q_4_CYSELF : STD_LOGIC; 
  signal Indic_Q_4_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_4_CYAND : STD_LOGIC; 
  signal Indic_Q_4_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_4_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_4_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_4_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_4_CYSELG : STD_LOGIC; 
  signal Indic_Q_4_G : STD_LOGIC; 
  signal Indic_Q_4_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_4_CLKINV : STD_LOGIC; 
  signal Indic_Q_6_DXMUX : STD_LOGIC; 
  signal Indic_Q_6_XORF : STD_LOGIC; 
  signal Indic_Q_6_CYINIT : STD_LOGIC; 
  signal Indic_Q_6_F : STD_LOGIC; 
  signal Indic_Q_6_DYMUX : STD_LOGIC; 
  signal Indic_Q_6_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_6_cyo : STD_LOGIC; 
  signal Indic_Q_6_CYSELF : STD_LOGIC; 
  signal Indic_Q_6_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_6_CYAND : STD_LOGIC; 
  signal Indic_Q_6_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_6_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_6_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_6_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_6_CYSELG : STD_LOGIC; 
  signal Indic_Q_6_G : STD_LOGIC; 
  signal Indic_Q_6_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_6_CLKINV : STD_LOGIC; 
  signal Indic_Q_8_DXMUX : STD_LOGIC; 
  signal Indic_Q_8_XORF : STD_LOGIC; 
  signal Indic_Q_8_CYINIT : STD_LOGIC; 
  signal Indic_Q_8_F : STD_LOGIC; 
  signal Indic_Q_8_DYMUX : STD_LOGIC; 
  signal Indic_Q_8_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_8_cyo : STD_LOGIC; 
  signal Indic_Q_8_CYSELF : STD_LOGIC; 
  signal Indic_Q_8_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_8_CYAND : STD_LOGIC; 
  signal Indic_Q_8_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_8_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_8_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_8_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_8_CYSELG : STD_LOGIC; 
  signal Indic_Q_8_G : STD_LOGIC; 
  signal Indic_Q_8_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_8_CLKINV : STD_LOGIC; 
  signal Indic_Q_10_DXMUX : STD_LOGIC; 
  signal Indic_Q_10_XORF : STD_LOGIC; 
  signal Indic_Q_10_CYINIT : STD_LOGIC; 
  signal Indic_Q_10_F : STD_LOGIC; 
  signal Indic_Q_10_DYMUX : STD_LOGIC; 
  signal Indic_Q_10_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_10_cyo : STD_LOGIC; 
  signal Indic_Q_10_CYSELF : STD_LOGIC; 
  signal Indic_Q_10_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_10_CYAND : STD_LOGIC; 
  signal Indic_Q_10_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_10_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_10_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_10_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_10_CYSELG : STD_LOGIC; 
  signal Indic_Q_10_G : STD_LOGIC; 
  signal Indic_Q_10_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_10_CLKINV : STD_LOGIC; 
  signal Indic_Q_12_DXMUX : STD_LOGIC; 
  signal Indic_Q_12_XORF : STD_LOGIC; 
  signal Indic_Q_12_CYINIT : STD_LOGIC; 
  signal Indic_Q_12_F : STD_LOGIC; 
  signal Indic_Q_12_DYMUX : STD_LOGIC; 
  signal Indic_Q_12_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_12_cyo : STD_LOGIC; 
  signal Indic_Q_12_CYSELF : STD_LOGIC; 
  signal Indic_Q_12_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_12_CYAND : STD_LOGIC; 
  signal Indic_Q_12_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_12_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_12_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_12_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_12_CYSELG : STD_LOGIC; 
  signal Indic_Q_12_G : STD_LOGIC; 
  signal Indic_Q_12_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_12_CLKINV : STD_LOGIC; 
  signal Indic_Q_14_DXMUX : STD_LOGIC; 
  signal Indic_Q_14_XORF : STD_LOGIC; 
  signal Indic_Q_14_CYINIT : STD_LOGIC; 
  signal Indic_Q_14_F : STD_LOGIC; 
  signal Indic_Q_14_DYMUX : STD_LOGIC; 
  signal Indic_Q_14_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_14_cyo : STD_LOGIC; 
  signal Indic_Q_14_CYSELF : STD_LOGIC; 
  signal Indic_Q_14_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_14_CYAND : STD_LOGIC; 
  signal Indic_Q_14_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_14_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_14_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_14_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_14_CYSELG : STD_LOGIC; 
  signal Indic_Q_14_G : STD_LOGIC; 
  signal Indic_Q_14_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_14_CLKINV : STD_LOGIC; 
  signal Indic_Q_16_DXMUX : STD_LOGIC; 
  signal Indic_Q_16_XORF : STD_LOGIC; 
  signal Indic_Q_16_CYINIT : STD_LOGIC; 
  signal Indic_Q_16_F : STD_LOGIC; 
  signal Indic_Q_16_DYMUX : STD_LOGIC; 
  signal Indic_Q_16_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_16_cyo : STD_LOGIC; 
  signal Indic_Q_16_CYSELF : STD_LOGIC; 
  signal Indic_Q_16_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_16_CYAND : STD_LOGIC; 
  signal Indic_Q_16_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_16_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_16_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_16_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_16_CYSELG : STD_LOGIC; 
  signal Indic_Q_16_G : STD_LOGIC; 
  signal Indic_Q_16_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_16_CLKINV : STD_LOGIC; 
  signal Indic_Q_18_DXMUX : STD_LOGIC; 
  signal Indic_Q_18_XORF : STD_LOGIC; 
  signal Indic_Q_18_CYINIT : STD_LOGIC; 
  signal Indic_Q_18_F : STD_LOGIC; 
  signal Indic_Q_18_DYMUX : STD_LOGIC; 
  signal Indic_Q_18_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_18_cyo : STD_LOGIC; 
  signal Indic_Q_18_CYSELF : STD_LOGIC; 
  signal Indic_Q_18_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_18_CYAND : STD_LOGIC; 
  signal Indic_Q_18_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_18_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_18_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_18_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_18_CYSELG : STD_LOGIC; 
  signal Indic_Q_18_G : STD_LOGIC; 
  signal Indic_Q_18_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_18_CLKINV : STD_LOGIC; 
  signal Indic_Q_20_DXMUX : STD_LOGIC; 
  signal Indic_Q_20_XORF : STD_LOGIC; 
  signal Indic_Q_20_CYINIT : STD_LOGIC; 
  signal Indic_Q_20_F : STD_LOGIC; 
  signal Indic_Q_20_DYMUX : STD_LOGIC; 
  signal Indic_Q_20_XORG : STD_LOGIC; 
  signal Indic_Q_LPM_COUNTER_1_n0000_20_cyo : STD_LOGIC; 
  signal Indic_Q_20_CYSELF : STD_LOGIC; 
  signal Indic_Q_20_CYMUXFAST : STD_LOGIC; 
  signal Indic_Q_20_CYAND : STD_LOGIC; 
  signal Indic_Q_20_FASTCARRY : STD_LOGIC; 
  signal Indic_Q_20_CYMUXG2 : STD_LOGIC; 
  signal Indic_Q_20_CYMUXF2 : STD_LOGIC; 
  signal Indic_Q_20_LOGIC_ZERO : STD_LOGIC; 
  signal Indic_Q_20_CYSELG : STD_LOGIC; 
  signal Indic_Q_20_G : STD_LOGIC; 
  signal Indic_Q_20_SRFFMUX : STD_LOGIC; 
  signal Indic_Q_20_CLKINV : STD_LOGIC; 
  signal Indic_Q_0_FFY_RST : STD_LOGIC; 
  signal Indic_Q_22_DXMUX : STD_LOGIC; 
  signal Indic_Q_22_XORF : STD_LOGIC; 
  signal Indic_Q_22_CYINIT : STD_LOGIC; 
  signal Indic_Q_22_rt : STD_LOGIC; 
  signal Indic_Q_22_CLKINV : STD_LOGIC; 
  signal TESTMODE_INBUF : STD_LOGIC; 
  signal A_0_ENABLE : STD_LOGIC; 
  signal A_0_GTS_OR_T : STD_LOGIC; 
  signal A_0_O : STD_LOGIC; 
  signal A_1_ENABLE : STD_LOGIC; 
  signal A_1_GTS_OR_T : STD_LOGIC; 
  signal A_1_O : STD_LOGIC; 
  signal Indy_ENABLE : STD_LOGIC; 
  signal Indy_GTS_OR_T : STD_LOGIC; 
  signal Indy_O : STD_LOGIC; 
  signal D_0_ENABLE : STD_LOGIC; 
  signal D_0_GTS_OR_T : STD_LOGIC; 
  signal D_0_O : STD_LOGIC; 
  signal D_0_T : STD_LOGIC; 
  signal D_0_INBUF : STD_LOGIC; 
  signal D_1_ENABLE : STD_LOGIC; 
  signal D_1_GTS_OR_T : STD_LOGIC; 
  signal D_1_O : STD_LOGIC; 
  signal D_1_T : STD_LOGIC; 
  signal D_1_INBUF : STD_LOGIC; 
  signal D_2_ENABLE : STD_LOGIC; 
  signal D_2_GTS_OR_T : STD_LOGIC; 
  signal D_2_O : STD_LOGIC; 
  signal D_2_T : STD_LOGIC; 
  signal D_2_INBUF : STD_LOGIC; 
  signal D_3_ENABLE : STD_LOGIC; 
  signal D_3_GTS_OR_T : STD_LOGIC; 
  signal D_3_O : STD_LOGIC; 
  signal D_3_T : STD_LOGIC; 
  signal D_3_INBUF : STD_LOGIC; 
  signal D_4_ENABLE : STD_LOGIC; 
  signal D_4_GTS_OR_T : STD_LOGIC; 
  signal D_4_O : STD_LOGIC; 
  signal D_4_T : STD_LOGIC; 
  signal D_4_INBUF : STD_LOGIC; 
  signal OKforCalc_ENABLE : STD_LOGIC; 
  signal OKforCalc_GTS_OR_T : STD_LOGIC; 
  signal OKforCalc_O : STD_LOGIC; 
  signal SDATA_ENABLE : STD_LOGIC; 
  signal SDATA_GTS_OR_T : STD_LOGIC; 
  signal SDATA_O : STD_LOGIC; 
  signal D_5_ENABLE : STD_LOGIC; 
  signal D_5_GTS_OR_T : STD_LOGIC; 
  signal D_5_O : STD_LOGIC; 
  signal D_5_T : STD_LOGIC; 
  signal D_5_INBUF : STD_LOGIC; 
  signal D_6_ENABLE : STD_LOGIC; 
  signal D_6_GTS_OR_T : STD_LOGIC; 
  signal D_6_O : STD_LOGIC; 
  signal D_6_T : STD_LOGIC; 
  signal D_6_INBUF : STD_LOGIC; 
  signal D_7_ENABLE : STD_LOGIC; 
  signal D_7_GTS_OR_T : STD_LOGIC; 
  signal D_7_O : STD_LOGIC; 
  signal D_7_T : STD_LOGIC; 
  signal D_7_INBUF : STD_LOGIC; 
  signal SCLK_INBUF : STD_LOGIC; 
  signal INDSTATE_0_ENABLE : STD_LOGIC; 
  signal INDSTATE_0_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_0_O : STD_LOGIC; 
  signal INDSTATE_1_ENABLE : STD_LOGIC; 
  signal INDSTATE_1_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_1_O : STD_LOGIC; 
  signal INDSTATE_2_ENABLE : STD_LOGIC; 
  signal INDSTATE_2_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_2_O : STD_LOGIC; 
  signal INDSTATE_3_ENABLE : STD_LOGIC; 
  signal INDSTATE_3_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_3_O : STD_LOGIC; 
  signal nIndy_ENABLE : STD_LOGIC; 
  signal nIndy_GTS_OR_T : STD_LOGIC; 
  signal nIndy_O : STD_LOGIC; 
  signal START_INBUF : STD_LOGIC; 
  signal OKforReset_ENABLE : STD_LOGIC; 
  signal OKforReset_GTS_OR_T : STD_LOGIC; 
  signal OKforReset_O : STD_LOGIC; 
  signal SCLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal test_A_0_F : STD_LOGIC; 
  signal test_A_0_DYMUX : STD_LOGIC; 
  signal test_A_0_G : STD_LOGIC; 
  signal test_A_0_SRFFMUX : STD_LOGIC; 
  signal test_A_0_CLKINV : STD_LOGIC; 
  signal test_OKforReset_DXMUX : STD_LOGIC; 
  signal test_OKforReset_F : STD_LOGIC; 
  signal test_OKforReset_G : STD_LOGIC; 
  signal test_OKforReset_SRFFMUX : STD_LOGIC; 
  signal test_OKforReset_CLKINV : STD_LOGIC; 
  signal CHOICE309_F : STD_LOGIC; 
  signal CHOICE309_G : STD_LOGIC; 
  signal test_state_FFd10_DXMUX : STD_LOGIC; 
  signal test_state_FFd10_F : STD_LOGIC; 
  signal test_state_FFd10_BXINVNOT : STD_LOGIC; 
  signal test_state_FFd10_DYMUX : STD_LOGIC; 
  signal test_state_FFd10_G : STD_LOGIC; 
  signal test_state_FFd10_SRFFMUX : STD_LOGIC; 
  signal test_state_FFd10_SRINVNOT : STD_LOGIC; 
  signal test_state_FFd10_CLKINV : STD_LOGIC; 
  signal test_ResetIndy_DXMUX : STD_LOGIC; 
  signal test_ResetIndy_F : STD_LOGIC; 
  signal test_ResetIndy_G : STD_LOGIC; 
  signal test_ResetIndy_SRFFMUX : STD_LOGIC; 
  signal test_ResetIndy_CLKINV : STD_LOGIC; 
  signal test_OKforCalc_DXMUX : STD_LOGIC; 
  signal test_OKforCalc_F : STD_LOGIC; 
  signal test_OKforCalc_G : STD_LOGIC; 
  signal test_OKforCalc_SRFFMUX : STD_LOGIC; 
  signal test_OKforCalc_CLKINV : STD_LOGIC; 
  signal test_state_FFd8_DXMUX : STD_LOGIC; 
  signal test_state_FFd8_F : STD_LOGIC; 
  signal test_state_FFd8_DYMUX : STD_LOGIC; 
  signal test_state_FFd8_G : STD_LOGIC; 
  signal test_state_FFd8_SRFFMUX : STD_LOGIC; 
  signal test_state_FFd8_SRINVNOT : STD_LOGIC; 
  signal test_state_FFd8_CLKINV : STD_LOGIC; 
  signal test_state_FFd4_DXMUX : STD_LOGIC; 
  signal test_state_FFd4_F : STD_LOGIC; 
  signal test_state_FFd4_DYMUX : STD_LOGIC; 
  signal test_state_FFd4_G : STD_LOGIC; 
  signal test_state_FFd4_SRFFMUX : STD_LOGIC; 
  signal test_state_FFd4_SRINVNOT : STD_LOGIC; 
  signal test_state_FFd4_CLKINV : STD_LOGIC; 
  signal Indic_Q_0_FFX_RST : STD_LOGIC; 
  signal test_state_FFd2_DXMUX : STD_LOGIC; 
  signal test_state_FFd2_DYMUX : STD_LOGIC; 
  signal test_state_FFd2_SRFFMUX : STD_LOGIC; 
  signal test_state_FFd2_SRINVNOT : STD_LOGIC; 
  signal test_state_FFd2_CLKINV : STD_LOGIC; 
  signal test_state_FFd6_DXMUX : STD_LOGIC; 
  signal test_state_FFd6_DYMUX : STD_LOGIC; 
  signal test_state_FFd6_SRFFMUX : STD_LOGIC; 
  signal test_state_FFd6_SRINVNOT : STD_LOGIC; 
  signal test_state_FFd6_CLKINV : STD_LOGIC; 
  signal INDSTATE_2_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_2_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal INDSTATE_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal INDSTATE_3_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_3_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal INDSTATE_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal Indic_Q_4_FFY_RST : STD_LOGIC; 
  signal Indic_Q_4_FFX_RST : STD_LOGIC; 
  signal Indic_Q_6_FFY_RST : STD_LOGIC; 
  signal Indic_Q_12_FFY_RST : STD_LOGIC; 
  signal Indic_Q_12_FFX_RST : STD_LOGIC; 
  signal Indic_Q_14_FFY_RST : STD_LOGIC; 
  signal Indic_Q_2_FFY_RST : STD_LOGIC; 
  signal Indic_Q_2_FFX_RST : STD_LOGIC; 
  signal Indic_Q_6_FFX_RST : STD_LOGIC; 
  signal Indic_Q_8_FFY_RST : STD_LOGIC; 
  signal Indic_Q_8_FFX_RST : STD_LOGIC; 
  signal Indic_Q_14_FFX_RST : STD_LOGIC; 
  signal Indic_Q_16_FFY_RST : STD_LOGIC; 
  signal Indic_Q_20_FFY_RST : STD_LOGIC; 
  signal Indic_Q_20_FFX_RST : STD_LOGIC; 
  signal Indic_Q_22_FFX_RST : STD_LOGIC; 
  signal Indic_Q_22_FFX_RSTAND : STD_LOGIC; 
  signal Indic_Q_10_FFY_RST : STD_LOGIC; 
  signal Indic_Q_10_FFX_RST : STD_LOGIC; 
  signal test_state_FFd2_FFX_RST : STD_LOGIC; 
  signal test_state_FFd6_FFY_RST : STD_LOGIC; 
  signal test_state_FFd6_FFX_RST : STD_LOGIC; 
  signal Indic_Q_16_FFX_RST : STD_LOGIC; 
  signal Indic_Q_18_FFY_RST : STD_LOGIC; 
  signal Indic_Q_18_FFX_RST : STD_LOGIC; 
  signal test_state_FFd2_FFY_RST : STD_LOGIC; 
  signal test_state_FFd8_FFY_RST : STD_LOGIC; 
  signal test_state_FFd8_FFX_RST : STD_LOGIC; 
  signal test_state_FFd4_FFY_RST : STD_LOGIC; 
  signal test_state_FFd4_FFX_RST : STD_LOGIC; 
  signal test_state_FFd10_FFY_RST : STD_LOGIC; 
  signal test_state_FFd10_FFX_SET : STD_LOGIC; 
  signal INDSTATE_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_0_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal INDSTATE_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal INDSTATE_1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal INDSTATE_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal A_1_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_0_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_0_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_1_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_1_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_2_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_2_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_3_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_3_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_4_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_4_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal SDATA_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_5_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_5_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_6_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_6_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal D_7_OUTPUT_TFF_T1INVNOT : STD_LOGIC; 
  signal D_7_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal nIndy_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal Indic_Q : STD_LOGIC_VECTOR ( 22 downto 0 ); 
  signal Indic_Q_n0000 : STD_LOGIC_VECTOR ( 22 downto 1 ); 
  signal test_A : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal test_n0012 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal test_INDSTATE : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  Indic_Q_0_LOGIC_ZERO_0 : X_ZERO
    port map (
      O => Indic_Q_0_LOGIC_ZERO
    );
  Indic_Q_0_LOGIC_ONE_1 : X_ONE
    port map (
      O => Indic_Q_0_LOGIC_ONE
    );
  Indic_Q_0_DXMUX_2 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indic_Q_N999,
      O => Indic_Q_0_DXMUX
    );
  Indic_Q_0_XUSED : X_BUF_PP