__projnav.log

VHDL source code for test machine.

# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity project
# -- Compiling architecture structural of project
# -- Loading entity sreg8
# -- Loading entity reg8
# -- Loading entity buf8
# -- Loading entity dec2to4
# -- Loading entity or1_ent
# -- Loading entity or2_ent
# -- Loading entity and_ent
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity indicator
# -- Compiling architecture behavioral of indicator
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fsm
# -- Compiling architecture struct of fsm
# -- Loading entity testmachine
# ** Warning: [1] fsm.vhd(91): (vcom-1134) Incompatible modes for port 'd' in component 'testmachine' when binding to entity 'testmachine'.
# A use of this default binding for this component instantiation will result in an elaboration error.
# ** Warning: [1] fsm.vhd(91): (vcom-1134) Incompatible modes for port 'sdata' in component 'testmachine' when binding to entity 'testmachine'.
# A use of this default binding for this component instantiation will result in an elaboration error.
# ** Warning: [1] fsm.vhd(91): (vcom-1134) Incompatible modes for port 'a' in component 'testmachine' when binding to entity 'testmachine'.
# A use of this default binding for this component instantiation will result in an elaboration error.
# ** Warning: [1] fsm.vhd(91): (vcom-1134) Incompatible modes for port 'wr' in component 'testmachine' when binding to entity 'testmachine'.
# A use of this default binding for this component instantiation will result in an elaboration error.
# ** Warning: [1] fsm.vhd(91): (vcom-1134) Incompatible modes for port 'rd' in component 'testmachine' when binding to entity 'testmachine'.
# A use of this default binding for this component instantiation will result in an elaboration error.
# ** Warning: [1] fsm.vhd(91): (vcom-1134) Incompatible modes for port 'resetcalc' in component 'testmachine' when binding to entity 'testmachine'.
# A use of this default binding for this component instantiation will result in an elaboration error.
# -- Loading entity project
# -- Loading entity indicator
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test1
# -- Compiling architecture testbench_arch of test1
# -- Loading entity fsm
# -- Compiling configuration fsm_cfg
# -- Loading entity test1
# -- Loading architecture testbench_arch of test1
# vsim -lib work -t 1ps test1 
# ** Error: License checkout has been disallowed because
# only one session is allowed to run on an uncounted nodelock
# license and an instance of ModelSim is already running with a
# nodelocked license on this machine
# Error loading design
Error loading design
ERROR: VSim failed to simulate annotated testbench

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.vhd in Library work.
Architecture behavioral of Entity indicator is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <indicator> (Architecture <behavioral>).
WARNING:Xst:819 - D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.vhd line 25: The following signals are missing in the process sensitivity list:
   Q.
Entity <indicator> analyzed. Unit <indicator> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <indicator>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.vhd.
    Found 23-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <indicator> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 23-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <indicator> ...
Loading device for application Xst from file '2v40.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block indicator, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      13  out of    256     5%  
 Number of Slice Flip Flops:            23  out of    512     4%  
 Number of 4 input LUTs:                24  out of    512     4%  
 Number of bonded IOBs:                  3  out of     88     3%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK_IN                             | BUFGP                  | 23    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.980ns (Maximum Frequency: 251.256MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.852ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\csht\final15.06.07\project\importantversion/_ngo -i -p xc2v40-fg256-5
indicator.ngc indicator.ngd 

Reading NGO file "D:/CShT/Final15.06.07/Project/ImportantVersion/indicator.ngc"
...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38236 kilobytes

Writing NGD file "indicator.ngd" ...

Writing NGDBUILD log file "indicator.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2v40fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          23 out of     512    4%
  Number of 4 input LUTs:               1 out of     512    1%
Logic Distribution:
  Number of occupied Slices:           12 out of     256    4%
  Number of Slices containing only related logic:      12 out of      12  100%
  Number of Slices containing unrelated logic:          0 out of      12    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             23 out of     512    4%
  Number used as logic:                 1
  Number used as a route-thru:         22

  Number of bonded IOBs:                4 out of      88    4%
  Number of GCLKs:                      1 out of      16    6%

Total equivalent gate count for design:  325
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "indicator_map.mrp" for details.
Completed process "Map".

Mapping Module indicator . . .
MAP command line:
map -intstyle ise -p xc2v40-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o indicator_map.ncd indicator.ngd indicator.pcf
Mapping Module indicator: DONE



Started process "Place & Route".





Constraints file: indicator.pcf

Loading device database for application Par from file "indicator_map.ncd".
   "indicator" is an NCD, version 2.38, device xc2v40, package fg256, speed -5
Loading device for application Par from file '2v40.nph' in environment
C:/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  PRODUCTION 1.120 2004-11-02.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             4 out of 88      4%
      Number of LOCed External IOBs    0 out of 4       0%

   Number of SLICEs                   12 out of 256     4%

   Number of BUFGMUXs                  1 out of 16      6%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

Phase 2.2

Phase 2.2 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.