__projnav.log

VHDL source code for test machine.

Reading NGO file "D:/CShT/Final15.06.07/Project/ImportantVersion/fsm.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "fsm.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38236 kilobytes

Writing NGD file "fsm.ngd" ...

Writing NGDBUILD log file "fsm.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2v40fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          37 out of     512    7%
  Number of 4 input LUTs:              17 out of     512    3%
Logic Distribution:
  Number of occupied Slices:           22 out of     256    8%
  Number of Slices containing only related logic:      22 out of      22  100%
  Number of Slices containing unrelated logic:          0 out of      22    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             39 out of     512    7%
  Number used as logic:                17
  Number used as a route-thru:         22

  Number of bonded IOBs:               22 out of      88   25%
    IOB Flip Flops:                     4
  Number of GCLKs:                      1 out of      16    6%

Total equivalent gate count for design:  589
Additional JTAG gate count for IOBs:  1,056
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "fsm_map.mrp" for details.
Completed process "Map".

Mapping Module fsm . . .
MAP command line:
map -intstyle ise -p xc2v40-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fsm_map.ncd fsm.ngd fsm.pcf
Mapping Module fsm: DONE



Started process "Place & Route".





Constraints file: fsm.pcf

Loading device database for application Par from file "fsm_map.ncd".
   "fsm" is an NCD, version 2.38, device xc2v40, package fg256, speed -5
Loading device for application Par from file '2v40.nph' in environment
C:/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  PRODUCTION 1.120 2004-11-02.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            22 out of 88     25%
      Number of LOCed External IOBs    0 out of 22      0%

   Number of SLICEs                   22 out of 256     8%

   Number of BUFGMUXs                  1 out of 16      6%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989707) REAL time: 0 secs 

Phase 2.2
.
Phase 2.2 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98ef44) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Phase 8.24
Phase 8.24 (Checksum:4c4b3f8) REAL time: 0 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 0 secs 

Writing design to file fsm.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 203 unrouted;       REAL time: 0 secs 

Phase 2: 164 unrouted;       REAL time: 2 secs 

Phase 3: 20 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|        SCLK_BUFGP       | BUFGMUX1S| No   |   25 |  0.155     |  0.571      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file fsm.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Tue Jun 26 12:51:26 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module fsm . . .
PAR command line: par -w -intstyle ise -ol std -t 1 fsm_map.ncd fsm.ncd fsm.pcf
PAR completed successfully



Started process "Generate Post-Place & Route Simulation Model".

Completed process "Generate Post-Place & Route Simulation Model".


Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/fsm.vhd in
Library work.
Entity <fsm> (Architecture <struct>) compiled.



Project Navigator Auto-Make Log File
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Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/fsm.vhd in
Library work.
Entity <fsm> (Architecture <struct>) compiled.



Project Navigator Auto-Make Log File
-------------------------------------

Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/fsm.vhd in
Library work.
Entity <fsm> (Architecture <struct>) compiled.



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 

# 5.8c

# do test1.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity testmachine
# -- Compiling architecture structural of testmachine
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity sreg8
# -- Compiling architecture behavioral of sreg8
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity reg8
# -- Compiling architecture behavioral of reg8
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity buf8
# -- Compiling architecture behavioral of buf8
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dec2to4
# -- Compiling architecture behavioral of dec2to4
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity or1_ent
# -- Compiling architecture behavioral of or1_ent
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity or2_ent
# -- Compiling architecture behavioral of or2_ent
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity and_ent
# -- Compiling architecture behavioral of and_ent