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VHDL source code for test machine.

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/sreg8.vhd in Library work.
Entity <sreg8> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/reg8.vhd in Library work.
Entity <reg8> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/buf8.vhd in Library work.
Entity <buf8> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/dec2to4.vhd in Library work.
Entity <dec2to4> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/or1_ent.vhd in Library work.
Entity <or1_ent> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/or2_ent.vhd in Library work.
Entity <or2_ent> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/and_ent.vhd in Library work.
Entity <and_ent> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/testmachine.vhd in Library work.
Entity <testmachine> (Architecture <Structural>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/project.vhd in Library work.
Entity <project> (Architecture <Structural>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/indicator.vhd in Library work.
Entity <indicator> (Architecture <Behavioral>) compiled.
Compiling vhdl file d:/csht/final15.06.07/project/importantversion/fsm.vhd in Library work.
Entity <fsm> (Architecture <struct>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fsm> (Architecture <struct>).
WARNING:Xst:754 - d:/csht/final15.06.07/project/importantversion/fsm.vhd line 77: Unconnected inout port 'RESET' of component 'testmachine'.
WARNING:Xst:753 - d:/csht/final15.06.07/project/importantversion/fsm.vhd line 93: Unconnected output port 'IRQ' of component 'project'.
Entity <fsm> analyzed. Unit <fsm> generated.

Analyzing Entity <testmachine> (Architecture <structural>).
INFO:Xst:1304 - Contents of register <SDATA> in unit <testmachine> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <RD> in unit <testmachine> never changes during circuit operation. The register is replaced by logic.
Entity <testmachine> analyzed. Unit <testmachine> generated.

Analyzing Entity <project> (Architecture <structural>).
Entity <project> analyzed. Unit <project> generated.

Analyzing Entity <sreg8> (Architecture <behavioral>).
WARNING:Xst:819 - d:/csht/final15.06.07/project/importantversion/sreg8.vhd line 26: The following signals are missing in the process sensitivity list:
   CLR, REG.
Entity <sreg8> analyzed. Unit <sreg8> generated.

Analyzing Entity <reg8> (Architecture <behavioral>).
Entity <reg8> analyzed. Unit <reg8> generated.

Analyzing Entity <buf8> (Architecture <behavioral>).
Entity <buf8> analyzed. Unit <buf8> generated.

Analyzing Entity <dec2to4> (Architecture <behavioral>).
Entity <dec2to4> analyzed. Unit <dec2to4> generated.

Analyzing Entity <or1_ent> (Architecture <behavioral>).
Entity <or1_ent> analyzed. Unit <or1_ent> generated.

Analyzing Entity <or2_ent> (Architecture <behavioral>).
Entity <or2_ent> analyzed. Unit <or2_ent> generated.

Analyzing Entity <and_ent> (Architecture <behavioral>).
Entity <and_ent> analyzed. Unit <and_ent> generated.

Analyzing Entity <Indicator> (Architecture <behavioral>).
WARNING:Xst:819 - d:/csht/final15.06.07/project/importantversion/indicator.vhd line 25: The following signals are missing in the process sensitivity list:
   Q.
Entity <Indicator> analyzed. Unit <Indicator> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <and_ent>.
    Related source file is d:/csht/final15.06.07/project/importantversion/and_ent.vhd.
Unit <and_ent> synthesized.


Synthesizing Unit <or2_ent>.
    Related source file is d:/csht/final15.06.07/project/importantversion/or2_ent.vhd.
Unit <or2_ent> synthesized.


Synthesizing Unit <or1_ent>.
    Related source file is d:/csht/final15.06.07/project/importantversion/or1_ent.vhd.
Unit <or1_ent> synthesized.


Synthesizing Unit <dec2to4>.
    Related source file is d:/csht/final15.06.07/project/importantversion/dec2to4.vhd.
    Found 1-of-4 decoder for signal <Y>.
    Summary:
	inferred   1 Decoder(s).
Unit <dec2to4> synthesized.


Synthesizing Unit <buf8>.
    Related source file is d:/csht/final15.06.07/project/importantversion/buf8.vhd.
    Found 8-bit tristate buffer for signal <Y>.
    Summary:
	inferred   8 Tristate(s).
Unit <buf8> synthesized.


Synthesizing Unit <reg8>.
    Related source file is d:/csht/final15.06.07/project/importantversion/reg8.vhd.
    Found 8-bit register for signal <Q>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <reg8> synthesized.


Synthesizing Unit <sreg8>.
    Related source file is d:/csht/final15.06.07/project/importantversion/sreg8.vhd.
    Found 9-bit register for signal <REG>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <sreg8> synthesized.


Synthesizing Unit <Indicator>.
    Related source file is d:/csht/final15.06.07/project/importantversion/indicator.vhd.
    Found 23-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <Indicator> synthesized.


Synthesizing Unit <project>.
    Related source file is d:/csht/final15.06.07/project/importantversion/project.vhd.
WARNING:Xst:646 - Signal <DEC_OUT<3:2>> is assigned but never used.
Unit <project> synthesized.


Synthesizing Unit <testmachine>.
    Related source file is d:/csht/final15.06.07/project/importantversion/testmachine.vhd.
WARNING:Xst:1777 - Inout <REG_OUT> is never used or assigned.
WARNING:Xst:1778 - Inout <RESET> is assigned but never used.
WARNING:Xst:1778 - Inout <A> is assigned but never used.
WARNING:Xst:1779 - Inout <D> is used but is never assigned.
WARNING:Xst:1778 - Inout <RD> is assigned but never used.
WARNING:Xst:1778 - Inout <ResetCalc> is assigned but never used.
WARNING:Xst:1778 - Inout <WR> is assigned but never used.
WARNING:Xst:1778 - Inout <SDATA> is assigned but never used.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 11                                             |
    | Inputs             | 1                                              |
    | Outputs            | 14                                             |
    | Clock              | SCLK (rising_edge)                             |
    | Reset              | START (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <OKforReset>.
    Found 1-bit register for signal <ResetIndy>.
    Found 1-bit register for signal <RESET>.
    Found 2-bit register for signal <A>.
    Found 1-bit register for signal <OKforCalc>.
    Found 1-bit register for signal <ResetCalc>.
    Found 1-bit register for signal <WR>.
    Found 4-bit register for signal <INDSTATE>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  12 D-type flip-flop(s).
Unit <testmachine> synthesized.


Synthesizing Unit <fsm>.
    Related source file is d:/csht/final15.06.07/project/importantversion/fsm.vhd.
Unit <fsm> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Counters                         : 1
 23-bit up counter                 : 1
# Registers                        : 28
 2-bit register                    : 1
 1-bit register                    : 25
 4-bit register                    : 1
 8-bit register                    : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <A_1> (without init value) is constant in block <testmachine>.
WARNING:Xst:1291 - FF/Latch <RESET> is unconnected in block <test>.

Optimizing unit <fsm> ...

Optimizing unit <testmachine> ...
Loading device for application Xst from file '2v40.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <device_sreg_REG_0> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_1> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_2> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_3> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_4> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_5> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_6> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_7> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_sreg_REG_8> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_5> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_4> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_3> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_2> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_1> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_0> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_7> (without init value) is constant in block <fsm>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <device_reg_Q_6> (without init value) is constant in block <fsm>.
WARNING:Xst:1291 - FF/Latch <test_RESET> is unconnected in block <fsm>.
WARNING:Xst:1291 - FF/Latch <test_WR> is unconnected in block <fsm>.
WARNING:Xst:1291 - FF/Latch <test_ResetCalc> is unconnected in block <fsm>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fsm, actual ratio is 9.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      25  out of    256     9%  
 Number of Slice Flip Flops:            41  out of    512     8%  
 Number of 4 input LUTs:                42  out of    512     8%  
 Number of bonded IOBs:                 21  out of     88    23%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
SCLK                               | BUFGP                  | 41    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.980ns (Maximum Frequency: 251.256MHz)
   Minimum input arrival time before clock: 2.904ns
   Maximum output required time after clock: 6.072ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\csht\final15.06.07\project\importantversion/_ngo -i -p xc2v40-fg256-5 fsm.ngc
fsm.ngd 

Reading NGO file "d:/csht/final15.06.07/project/importantversion/fsm.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38236 kilobytes

Writing NGD file "fsm.ngd" ...