fsm.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm is

	port( SCLK,TESTMODE         : in std_logic;
			START                 : in std_logic;
			INDSTATE		          : out std_logic_vector(3 downto 0);
			OKforCalc, OKforReset : out std_logic;	 
			Indy, nIndy           : out std_logic;
			SDATA						 : inout std_logic;
			A 		                : inout std_logic_vector (1 downto 0);
			D		                : inout std_logic_vector (7 downto 0)
		 );

end fsm;

architecture struct of fsm is

component testmachine
	port( SCLK			  : in std_logic;
			START			  : in std_logic;
			TESTMODE		  : in std_logic;
			INDSTATE		  : out std_logic_vector(3 downto 0);
			D		        : in std_logic_vector (7 downto 0);
			REG_OUT		  : inout std_logic_vector (7 downto 0);
			SDATA			  : out std_logic;
			A 		        : out std_logic_vector (1 downto 0);
			WR 	        : out std_logic;
			RD		        : out std_logic;
			OKforCalc	  : out std_logic;
			OKforReset    : out std_logic;
			ResetIndy	  : out std_logic;
			ResetCalc     : out std_logic
			);

end component;

component project
	port ( 	A 		  : in std_logic_vector (1 downto 0);
				SDATA	  : in std_logic;
				SCLK 	  : in std_logic;
 				RESET   : in std_logic ;
				WR 	  : in std_logic;
				RD		  : in std_logic;
				D		  : out std_logic_vector (7 downto 0);
				REG_OUT : inout std_logic_vector (7 downto 0)
--				IRQ	  : out std_logic	
			   );

	end component;

component Indicator
	port ( RESET  : in std_logic;
			 CLK_IN : in std_logic;
			 Indy	  : out std_logic;
			 nIndy  : out std_logic
			);

	end component;

signal WR 	     : std_logic;
signal RD		  : std_logic;
signal ResetIndy : std_logic;
signal ResetCalc : std_logic;
signal REG_OUT   : std_logic_vector (7 downto 0);

begin

	test: testmachine port map ( SCLK=> SCLK,
										  START=> START,
										  TESTMODE=> TESTMODE,
										  INDSTATE=> INDSTATE,
										  D=> D,
										  REG_OUT=> REG_OUT,
										  SDATA=> SDATA,
										  A=> A,
										  WR=> WR,
										  RD=> RD,
										  OKforCalc=>OKforCalc,
										  ResetIndy=> ResetIndy,
   									  ResetCalc=> ResetCalc,
   									  OKforReset=> OKforReset
										  );

	 device: project port map (  A=> A,
										  SDATA=> SDATA,
				                    SCLK=> SCLK,
 				                    RESET=> ResetCalc,
				                    WR=> WR,
				                    RD=> RD,
				                    D=> D,
				                    REG_OUT=> REG_OUT
--				                    IRQ=> REG_OUT
										);

	Indic: Indicator port map ( RESET=> ResetIndy,
										 CLK_IN=> SCLK,
										 Indy=> Indy,
										 nIndy=> nIndy
										);

end struct;