testmachine_timesim.vhd

VHDL source code for test machine.

      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => INDSTATE_1_OUTPUT_OTCLK1INV
    );
  INDSTATE_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_1,
      O => INDSTATE_1_O
    );
  INDSTATE_1_OUTPUT_OFF_O1INV_81 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n0012(1),
      O => INDSTATE_1_OUTPUT_OFF_O1INV
    );
  INDSTATE_1_82 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => INDSTATE_1_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => INDSTATE_1_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => INDSTATE_1_OUTPUT_OFF_OFF1_RST,
      O => INDSTATE_1
    );
  INDSTATE_1_OUTPUT_OFF_OFF1_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => INDSTATE_1_OUTPUT_OFF_OFF1_RST
    );
  INDSTATE_2_OUTPUT_OTCLK1INV_83 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => INDSTATE_2_OUTPUT_OTCLK1INV
    );
  INDSTATE_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_2,
      O => INDSTATE_2_O
    );
  INDSTATE_2_OUTPUT_OFF_OSR_USED_84 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd3,
      O => INDSTATE_2_OUTPUT_OFF_OSR_USED
    );
  INDSTATE_2_OUTPUT_OFF_O1INV_85 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => N3045,
      O => INDSTATE_2_OUTPUT_OFF_O1INV
    );
  INDSTATE_2_86 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => INDSTATE_2_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => INDSTATE_2_OUTPUT_OTCLK1INV,
      SET => GSR,
      RST => GND,
      SSET => INDSTATE_2_OUTPUT_OFF_OSR_USED,
      SRST => GND,
      O => INDSTATE_2
    );
  INDSTATE_3_OUTPUT_OTCLK1INV_87 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => INDSTATE_3_OUTPUT_OTCLK1INV
    );
  INDSTATE_3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_3,
      O => INDSTATE_3_O
    );
  INDSTATE_3_OUTPUT_OFF_OSR_USED_88 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd1,
      O => INDSTATE_3_OUTPUT_OFF_OSR_USED
    );
  INDSTATE_3_OUTPUT_OFF_O1INV_89 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd4,
      O => INDSTATE_3_OUTPUT_OFF_O1INV
    );
  INDSTATE_3_90 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => INDSTATE_3_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => INDSTATE_3_OUTPUT_OTCLK1INV,
      SET => GSR,
      RST => GND,
      SSET => INDSTATE_3_OUTPUT_OFF_OSR_USED,
      SRST => GND,
      O => INDSTATE_3
    );
  Q_n001311 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => ResetCalc_OBUF,
      ADR1 => state_FFd9,
      ADR2 => state_FFd4_In,
      ADR3 => Q_n0012(1),
      O => ResetCalc_OBUF_G
    );
  Q_n0016_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => state_FFd1,
      ADR1 => state_FFd5,
      ADR2 => state_FFd8,
      ADR3 => state_FFd9,
      O => ResetIndy_OBUF_G
    );
  ResetCalc_91 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => ResetCalc_OBUF_DYMUX,
      CE => VCC,
      CLK => ResetCalc_OBUF_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => ResetCalc_OBUF_SRFFMUX,
      SRST => GND,
      O => ResetCalc_OBUF
    );
  Q_n0014641 : X_LUT4
    generic map(
      INIT => X"F0E0"
    )
    port map (
      ADR0 => Q_n0012(1),
      ADR1 => N845,
      ADR2 => OKforCalc_OBUF,
      ADR3 => state_FFd4_In,
      O => OKforCalc_OBUF_G
    );
  state_Out1311 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => state_FFd9,
      ADR1 => state_FFd8,
      ADR2 => state_FFd4,
      ADR3 => state_FFd2,
      O => ResetCalc_OBUF_F
    );
  Q_n00161 : X_LUT4
    generic map(
      INIT => X"AAA0"
    )
    port map (
      ADR0 => ResetIndy_OBUF,
      ADR1 => VCC,
      ADR2 => Q_n0012(1),
      ADR3 => Q_n0016_SW0_O,
      O => ResetIndy_OBUF_F
    );
  state_FFd3_92 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd4_DYMUX,
      CE => VCC,
      CLK => state_FFd4_CLKINV,
      SET => GND,
      RST => state_FFd4_FFY_RST,
      O => state_FFd3
    );
  state_FFd4_FFY_RSTOR : X_OR2
    port map (
      I0 => state_FFd4_SRFFMUX,
      I1 => GSR,
      O => state_FFd4_FFY_RST
    );
  state_FFd4_In1 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => state_FFd4,
      ADR2 => state_FFd1,
      ADR3 => state_FFd5,
      O => state_FFd4_F
    );
  state_FFd4_93 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd4_DXMUX,
      CE => VCC,
      CLK => state_FFd4_CLKINV,
      SET => GND,
      RST => state_FFd4_FFX_RST,
      O => state_FFd4
    );
  state_FFd4_FFX_RSTOR : X_OR2
    port map (
      I0 => state_FFd4_SRFFMUX,
      I1 => GSR,
      O => state_FFd4_FFX_RST
    );
  state_FFd5_94 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd6_DYMUX,
      CE => VCC,
      CLK => state_FFd6_CLKINV,
      SET => GND,
      RST => state_FFd6_FFY_RST,
      O => state_FFd5
    );
  state_FFd6_FFY_RSTOR : X_OR2
    port map (
      I0 => state_FFd6_SRFFMUX,
      I1 => GSR,
      O => state_FFd6_FFY_RST
    );
  state_FFd6_95 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd6_DXMUX,
      CE => VCC,
      CLK => state_FFd6_CLKINV,
      SET => GND,
      RST => state_FFd6_FFX_RST,
      O => state_FFd6
    );
  state_FFd6_FFX_RSTOR : X_OR2
    port map (
      I0 => state_FFd6_SRFFMUX,
      I1 => GSR,
      O => state_FFd6_FFX_RST
    );
  state_FFd8_In1 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => state_FFd10,
      ADR2 => VCC,
      ADR3 => TESTMODE_IBUF,
      O => state_FFd7_G
    );
  Q_n001415 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => D_0_IBUF,
      ADR1 => D_5_IBUF,
      ADR2 => D_6_IBUF,
      ADR3 => D_1_IBUF,
      O => CHOICE316_F
    );
  Q_n001430 : X_LUT4
    generic map(
      INIT => X"1010"
    )
    port map (
      ADR0 => D_3_IBUF,
      ADR1 => D_2_IBUF,
      ADR2 => CHOICE323,
      ADR3 => VCC,
      O => CHOICE326_G
    );
  state_FFd8_96 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd7_DYMUX,
      CE => VCC,
      CLK => state_FFd7_CLKINV,
      SET => GND,
      RST => state_FFd7_FFY_RST,
      O => state_FFd8
    );
  state_FFd7_FFY_RSTOR : X_OR2
    port map (
      I0 => state_FFd7_SRFFMUX,
      I1 => GSR,
      O => state_FFd7_FFY_RST
    );
  ResetIndy_97 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => ResetIndy_OBUF_DXMUX,
      CE => VCC,
      CLK => ResetIndy_OBUF_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => ResetIndy_OBUF_SRFFMUX,
      SRST => GND,
      O => ResetIndy_OBUF
    );
  Q_n001911 : X_LUT4
    generic map(
      INIT => X"FE00"
    )
    port map (
      ADR0 => state_FFd4_In,
      ADR1 => Q_n0012(1),
      ADR2 => state_FFd8,
      ADR3 => WR_OBUF,
      O => RESET_OBUF_G
    );
  OKforCalc_98 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => OKforCalc_OBUF_DYMUX,
      CE => VCC,
      CLK => OKforCalc_OBUF_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => OKforCalc_OBUF_SRFFMUX,
      SRST => GND,
      O => OKforCalc_OBUF
    );
  Ker8431 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => state_FFd8,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => state_FFd9,
      O => OKforReset_OBUF_G
    );
  state_Out121 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => state_FFd6,
      ADR1 => state_FFd3,
      ADR2 => state_FFd7,
      ADR3 => state_FFd2,
      O => Q_n0012_1_F
    );
  WR_99 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => RESET_OBUF_DYMUX,
      CE => VCC,
      CLK => RESET_OBUF_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => RESET_OBUF_SRFFMUX,
      SRST => GND,
      O => WR_OBUF
    );
  Q_n001811 : X_LUT4
    generic map(
      INIT => X"F0E0"
    )
    port map (
      ADR0 => Q_n0012(1),
      ADR1 => state_FFd4_In,
      ADR2 => RESET_OBUF,
      ADR3 => state_FFd8,
      O => RESET_OBUF_F
    );
  RESET_100 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => RESET_OBUF_DXMUX,
      CE => VCC,
      CLK => RESET_OBUF_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => RESET_OBUF_SRFFMUX,
      SRST => GND,
      O => RESET_OBUF
    );
  Q_n0015_SW181 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => OKforReset_OBUF,
      ADR1 => state_FFd4_In,
      ADR2 => N845,
      ADR3 => Q_n0012(1),
      O => OKforReset_OBUF_F
    );
  Q_n0017_0_11 : X_LUT4
    generic map(
      INIT => X"F0E0"
    )
    port map (
      ADR0 => Q_n0012(1),
      ADR1 => state_FFd8,
      ADR2 => A_0,
      ADR3 => state_FFd4_In,
      O => A_0_G
    );
  OKforReset_101 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => OKforReset_OBUF_DXMUX,
      CE => VCC,
      CLK => OKforReset_OBUF_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => OKforReset_OBUF_SRFFMUX,
      SRST => GND,
      O => OKforReset_OBUF
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  PWR_VCC_1_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1_0
    );
  PWR_VCC_2_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1_1
    );
  TESTMODE_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => TESTMODE_INBUF,
      O => TESTMODE_IBUF
    );
  A_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_0,
      O => A_0_O
    );
  A_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_1_OUTPUT_OFF_O1INVNOT,
      O => A_1_O
    );
  A_1_OUTPUT_OFF_O1INV : X_INV
    port map (
      I => GLOBAL_LOGIC1_1,
      O => A_1_OUTPUT_OFF_O1INVNOT
    );
  ResetIndy_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetIndy_OBUF,
      O => ResetIndy_O
    );
  RD_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RD_OUTPUT_OFF_O1INVNOT,
      O => RD_O
    );
  RD_OUTPUT_OFF_O1INV : X_INV
    port map (
      I => GLOBAL_LOGIC1_1,
      O => RD_OUTPUT_OFF_O1INVNOT
    );
  WR_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => WR_OBUF,
      O => WR_O
    );
  D_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_0_INBUF,
      O => D_0_IBUF
    );
  D_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_1_INBUF,
      O => D_1_IBUF
    );
  D_2_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_2_INBUF,
      O => D_2_IBUF
    );
  D_3_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_3_INBUF,
      O => D_3_IBUF
    );
  D_4_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_4_INBUF,
      O => D_4_IBUF
    );
  SDATA_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SDATA_OUTPUT_OFF_O1INVNOT,
      O => SDATA_O
    );
  SDATA_OUTPUT_OFF_O1INV : X_INV
    port map (
      I => GLOBAL_LOGIC1_1,
      O => SDATA_OUTPUT_OFF_O1INVNOT
    );
  OKforCalc_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforCalc_OBUF,
      O => OKforCalc_O
    );
  D_5_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_5_INBUF,
      O => D_5_IBUF
    );
  D_6_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_6_INBUF,
      O => D_6_IBUF
    );
  D_7_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_7_INBUF,
      O => D_7_IBUF
    );
  ResetCalc_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetCalc_OBUF,
      O => ResetCalc_O
    );
  SCLK_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_INBUF,
      O => SCLK_BUFGP_IBUFG
    );
  OKforReset_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforReset_OBUF,
      O => OKforReset_O
    );
  RESET_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RESET_OBUF,
      O => RESET_O
    );
  START_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => START_INBUF,
      O => START_IBUF
    );
  NlwBlock_testmachine_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_testmachine_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;