testmachine_timesim.vhd

VHDL source code for test machine.

  ResetCalc_OBUF_SRFFMUX_32 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd8,
      O => ResetCalc_OBUF_SRFFMUX
    );
  ResetCalc_OBUF_CLKINV_33 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => ResetCalc_OBUF_CLKINV
    );
  ResetIndy_OBUF_DXMUX_34 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n00161_O,
      O => ResetIndy_OBUF_DXMUX
    );
  ResetIndy_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetIndy_OBUF_F,
      O => Q_n00161_O
    );
  ResetIndy_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetIndy_OBUF_G,
      O => Q_n0016_SW0_O
    );
  ResetIndy_OBUF_SRFFMUX_35 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd10,
      O => ResetIndy_OBUF_SRFFMUX
    );
  ResetIndy_OBUF_CLKINV_36 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => ResetIndy_OBUF_CLKINV
    );
  OKforCalc_OBUF_DYMUX_37 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n0014641_O,
      O => OKforCalc_OBUF_DYMUX
    );
  OKforCalc_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforCalc_OBUF_G,
      O => Q_n0014641_O
    );
  OKforCalc_OBUF_SRFFMUX_38 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => CHOICE326,
      O => OKforCalc_OBUF_SRFFMUX
    );
  OKforCalc_OBUF_CLKINV_39 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => OKforCalc_OBUF_CLKINV
    );
  RESET_OBUF_DXMUX_40 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n001811_O,
      O => RESET_OBUF_DXMUX
    );
  RESET_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RESET_OBUF_F,
      O => Q_n001811_O
    );
  RESET_OBUF_DYMUX_41 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n001911_O,
      O => RESET_OBUF_DYMUX
    );
  RESET_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RESET_OBUF_G,
      O => Q_n001911_O
    );
  RESET_OBUF_SRFFMUX_42 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd9,
      O => RESET_OBUF_SRFFMUX
    );
  RESET_OBUF_CLKINV_43 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => RESET_OBUF_CLKINV
    );
  OKforReset_OBUF_DXMUX_44 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n0015_SW181_O,
      O => OKforReset_OBUF_DXMUX
    );
  OKforReset_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforReset_OBUF_F,
      O => Q_n0015_SW181_O
    );
  OKforReset_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforReset_OBUF_G,
      O => N845
    );
  OKforReset_OBUF_SRFFMUX_45 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => CHOICE306,
      O => OKforReset_OBUF_SRFFMUX
    );
  OKforReset_OBUF_CLKINV_46 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => OKforReset_OBUF_CLKINV
    );
  A_0_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_0_F,
      O => N3045
    );
  A_0_DYMUX_47 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n0017_0_11_O,
      O => A_0_DYMUX
    );
  A_0_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_0_G,
      O => Q_n0017_0_11_O
    );
  A_0_SRFFMUX_48 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd9,
      O => A_0_SRFFMUX
    );
  A_0_CLKINV_49 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => A_0_CLKINV
    );
  state_FFd10_DXMUX_50 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd10_BXINVNOT,
      O => state_FFd10_DXMUX
    );
  state_FFd10_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd10_F,
      O => CHOICE306
    );
  state_FFd10_BXINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => state_FFd10_BXINVNOT
    );
  state_FFd10_DYMUX_51 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd9_In,
      O => state_FFd10_DYMUX
    );
  state_FFd10_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd10_G,
      O => state_FFd9_In
    );
  state_FFd10_SRFFMUX_52 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd10_SRINVNOT,
      O => state_FFd10_SRFFMUX
    );
  state_FFd10_SRINV : X_INV
    port map (
      I => START_IBUF,
      O => state_FFd10_SRINVNOT
    );
  state_FFd10_CLKINV_53 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => state_FFd10_CLKINV
    );
  Q_n0012_1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n0012_1_F,
      O => Q_n0012(1)
    );
  state_FFd2_DXMUX_54 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd3,
      O => state_FFd2_DXMUX
    );
  state_FFd2_DYMUX_55 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd2,
      O => state_FFd2_DYMUX
    );
  state_FFd2_SRFFMUX_56 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd2_SRINVNOT,
      O => state_FFd2_SRFFMUX
    );
  state_FFd2_SRINV : X_INV
    port map (
      I => START_IBUF,
      O => state_FFd2_SRINVNOT
    );
  state_FFd2_CLKINV_57 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => state_FFd2_CLKINV
    );
  state_FFd4_DXMUX_58 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd4_In,
      O => state_FFd4_DXMUX
    );
  state_FFd4_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd4_F,
      O => state_FFd4_In
    );
  state_FFd4_DYMUX_59 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd8,
      O => state_FFd4_DYMUX
    );
  state_FFd4_SRFFMUX_60 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd4_SRINVNOT,
      O => state_FFd4_SRFFMUX
    );
  state_FFd4_SRINV : X_INV
    port map (
      I => START_IBUF,
      O => state_FFd4_SRINVNOT
    );
  state_FFd4_CLKINV_61 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => state_FFd4_CLKINV
    );
  state_FFd6_DXMUX_62 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd7,
      O => state_FFd6_DXMUX
    );
  state_FFd6_DYMUX_63 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd6,
      O => state_FFd6_DYMUX
    );
  state_FFd6_SRFFMUX_64 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd6_SRINVNOT,
      O => state_FFd6_SRFFMUX
    );
  state_FFd6_SRINV : X_INV
    port map (
      I => START_IBUF,
      O => state_FFd6_SRINVNOT
    );
  state_FFd6_CLKINV_65 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => state_FFd6_CLKINV
    );
  state_FFd7_DXMUX_66 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd9,
      O => state_FFd7_DXMUX
    );
  state_FFd7_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd7_F,
      O => CHOICE323
    );
  state_FFd7_DYMUX_67 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd8_In,
      O => state_FFd7_DYMUX
    );
  state_FFd7_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd7_G,
      O => state_FFd8_In
    );
  state_FFd7_SRFFMUX_68 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd7_SRINVNOT,
      O => state_FFd7_SRFFMUX
    );
  state_FFd7_SRINV : X_INV
    port map (
      I => START_IBUF,
      O => state_FFd7_SRINVNOT
    );
  state_FFd7_CLKINV_69 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => state_FFd7_CLKINV
    );
  CHOICE326_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => CHOICE326_F,
      O => CHOICE326
    );
  CHOICE326_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => CHOICE326_G,
      O => CHOICE324
    );
  CHOICE316_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => CHOICE316_F,
      O => CHOICE316
    );
  Q_n001449 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => CHOICE316,
      ADR1 => VCC,
      ADR2 => CHOICE324,
      ADR3 => state_FFd4,
      O => CHOICE326_F
    );
  Q_n001427 : X_LUT4
    generic map(
      INIT => X"1100"
    )
    port map (
      ADR0 => D_4_IBUF,
      ADR1 => D_7_IBUF,
      ADR2 => VCC,
      ADR3 => TESTMODE_IBUF,
      O => state_FFd7_F
    );
  state_FFd7_70 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd7_DXMUX,
      CE => VCC,
      CLK => state_FFd7_CLKINV,
      SET => GND,
      RST => state_FFd7_FFX_RST,
      O => state_FFd7
    );
  state_FFd7_FFX_RSTOR : X_OR2
    port map (
      I0 => state_FFd7_SRFFMUX,
      I1 => GSR,
      O => state_FFd7_FFX_RST
    );
  state_FFd9_In1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => TESTMODE_IBUF,
      ADR3 => state_FFd10,
      O => state_FFd10_G
    );
  A_0_71 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => A_0_DYMUX,
      CE => VCC,
      CLK => A_0_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => A_0_SRFFMUX,
      SRST => GND,
      O => A_0
    );
  state_Out1111 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => state_FFd5,
      ADR1 => state_FFd8,
      ADR2 => state_FFd2,
      ADR3 => VCC,
      O => A_0_F
    );
  state_FFd9_72 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd10_DYMUX,
      CE => VCC,
      CLK => state_FFd10_CLKINV,
      SET => GND,
      RST => state_FFd10_FFY_RST,
      O => state_FFd9
    );
  state_FFd10_FFY_RSTOR : X_OR2
    port map (
      I0 => state_FFd10_SRFFMUX,
      I1 => GSR,
      O => state_FFd10_FFY_RST
    );
  Q_n0015_SW15 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => state_FFd4,
      ADR3 => TESTMODE_IBUF,
      O => state_FFd10_F
    );
  state_FFd10_73 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => state_FFd10_DXMUX,
      CE => VCC,
      CLK => state_FFd10_CLKINV,
      SET => state_FFd10_FFX_SET,
      RST => GND,
      O => state_FFd10
    );
  state_FFd10_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => state_FFd10_SRFFMUX,
      O => state_FFd10_FFX_SET
    );
  state_FFd1_74 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd2_DYMUX,
      CE => VCC,
      CLK => state_FFd2_CLKINV,
      SET => GND,
      RST => state_FFd2_FFY_RST,
      O => state_FFd1
    );
  state_FFd2_FFY_RSTOR : X_OR2
    port map (
      I0 => state_FFd2_SRFFMUX,
      I1 => GSR,
      O => state_FFd2_FFY_RST
    );
  state_FFd2_75 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_FFd2_DXMUX,
      CE => VCC,
      CLK => state_FFd2_CLKINV,
      SET => GND,
      RST => state_FFd2_FFX_RST,
      O => state_FFd2
    );
  state_FFd2_FFX_RSTOR : X_OR2
    port map (
      I0 => state_FFd2_SRFFMUX,
      I1 => GSR,
      O => state_FFd2_FFX_RST
    );
  INDSTATE_0_OUTPUT_OTCLK1INV_76 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK_BUFGP,
      O => INDSTATE_0_OUTPUT_OTCLK1INV
    );
  INDSTATE_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_0,
      O => INDSTATE_0_O
    );
  INDSTATE_0_OUTPUT_OFF_OSR_USED_77 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => state_FFd6,
      O => INDSTATE_0_OUTPUT_OFF_OSR_USED
    );
  INDSTATE_0_OUTPUT_OFF_O1INV_78 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => N3067,
      O => INDSTATE_0_OUTPUT_OFF_O1INV
    );
  INDSTATE_0_79 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => INDSTATE_0_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => INDSTATE_0_OUTPUT_OTCLK1INV,
      SET => GSR,
      RST => GND,
      SSET => INDSTATE_0_OUTPUT_OFF_OSR_USED,
      SRST => GND,
      O => INDSTATE_0
    );
  INDSTATE_1_OUTPUT_OTCLK1INV_80 : X_BUF_PP
    generic map(