testmachine_timesim.vhd

VHDL source code for test machine.

-- Xilinx Vhdl netlist produced by netgen application (version G.38)
-- Command       : -intstyle ise -s 5 -pcf testmachine.pcf -ngm testmachine.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim testmachine.ncd testmachine_timesim.vhd 
-- Input file    : testmachine.ncd
-- Output file   : testmachine_timesim.vhd
-- Design name   : testmachine
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2v40fg256-5 (PRODUCTION 1.120 2004-11-02, STEPPING 1)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity testmachine is
  port (
    OKforCalc : out STD_LOGIC; 
    ResetIndy : out STD_LOGIC; 
    OKforReset : out STD_LOGIC; 
    SDATA : inout STD_LOGIC; 
    WR : inout STD_LOGIC; 
    ResetCalc : inout STD_LOGIC; 
    RD : inout STD_LOGIC; 
    RESET : inout STD_LOGIC; 
    TESTMODE : in STD_LOGIC := 'X'; 
    SCLK : in STD_LOGIC := 'X'; 
    START : in STD_LOGIC := 'X'; 
    INDSTATE : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    A : inout STD_LOGIC_VECTOR ( 1 downto 0 ); 
    REG_OUT : inout STD_LOGIC_VECTOR ( 7 downto 0 ); 
    D : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end testmachine;

architecture Structure of testmachine is
  signal TESTMODE_IBUF : STD_LOGIC; 
  signal A_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal ResetIndy_OBUF : STD_LOGIC; 
  signal WR_OBUF : STD_LOGIC; 
  signal D_0_IBUF : STD_LOGIC; 
  signal D_1_IBUF : STD_LOGIC; 
  signal D_2_IBUF : STD_LOGIC; 
  signal D_3_IBUF : STD_LOGIC; 
  signal D_4_IBUF : STD_LOGIC; 
  signal OKforCalc_OBUF : STD_LOGIC; 
  signal D_5_IBUF : STD_LOGIC; 
  signal D_6_IBUF : STD_LOGIC; 
  signal D_7_IBUF : STD_LOGIC; 
  signal ResetCalc_OBUF : STD_LOGIC; 
  signal SCLK_BUFGP_IBUFG : STD_LOGIC; 
  signal state_FFd6 : STD_LOGIC; 
  signal SCLK_BUFGP : STD_LOGIC; 
  signal N3067 : STD_LOGIC; 
  signal OKforReset_OBUF : STD_LOGIC; 
  signal state_FFd3 : STD_LOGIC; 
  signal N3045 : STD_LOGIC; 
  signal state_FFd1 : STD_LOGIC; 
  signal state_FFd4 : STD_LOGIC; 
  signal RESET_OBUF : STD_LOGIC; 
  signal START_IBUF : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal state_FFd8 : STD_LOGIC; 
  signal state_FFd2 : STD_LOGIC; 
  signal state_FFd9 : STD_LOGIC; 
  signal state_FFd4_In : STD_LOGIC; 
  signal Q_n001311_O : STD_LOGIC; 
  signal state_FFd10 : STD_LOGIC; 
  signal Q_n0016_SW0_O : STD_LOGIC; 
  signal state_FFd5 : STD_LOGIC; 
  signal Q_n00161_O : STD_LOGIC; 
  signal CHOICE326 : STD_LOGIC; 
  signal N845 : STD_LOGIC; 
  signal Q_n0014641_O : STD_LOGIC; 
  signal Q_n001811_O : STD_LOGIC; 
  signal Q_n001911_O : STD_LOGIC; 
  signal CHOICE306 : STD_LOGIC; 
  signal Q_n0015_SW181_O : STD_LOGIC; 
  signal Q_n0017_0_11_O : STD_LOGIC; 
  signal state_FFd9_In : STD_LOGIC; 
  signal state_FFd7 : STD_LOGIC; 
  signal CHOICE323 : STD_LOGIC; 
  signal state_FFd8_In : STD_LOGIC; 
  signal CHOICE316 : STD_LOGIC; 
  signal CHOICE324 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_1 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal TESTMODE_INBUF : STD_LOGIC; 
  signal A_0_ENABLE : STD_LOGIC; 
  signal A_0_GTS_OR_T : STD_LOGIC; 
  signal A_0_O : STD_LOGIC; 
  signal A_1_ENABLE : STD_LOGIC; 
  signal A_1_GTS_OR_T : STD_LOGIC; 
  signal A_1_O : STD_LOGIC; 
  signal ResetIndy_ENABLE : STD_LOGIC; 
  signal ResetIndy_GTS_OR_T : STD_LOGIC; 
  signal ResetIndy_O : STD_LOGIC; 
  signal RD_ENABLE : STD_LOGIC; 
  signal RD_GTS_OR_T : STD_LOGIC; 
  signal RD_O : STD_LOGIC; 
  signal WR_ENABLE : STD_LOGIC; 
  signal WR_GTS_OR_T : STD_LOGIC; 
  signal WR_O : STD_LOGIC; 
  signal D_0_INBUF : STD_LOGIC; 
  signal D_1_INBUF : STD_LOGIC; 
  signal D_2_INBUF : STD_LOGIC; 
  signal D_3_INBUF : STD_LOGIC; 
  signal D_4_INBUF : STD_LOGIC; 
  signal SDATA_ENABLE : STD_LOGIC; 
  signal SDATA_GTS_OR_T : STD_LOGIC; 
  signal SDATA_O : STD_LOGIC; 
  signal OKforCalc_ENABLE : STD_LOGIC; 
  signal OKforCalc_GTS_OR_T : STD_LOGIC; 
  signal OKforCalc_O : STD_LOGIC; 
  signal D_5_INBUF : STD_LOGIC; 
  signal D_6_INBUF : STD_LOGIC; 
  signal D_7_INBUF : STD_LOGIC; 
  signal ResetCalc_ENABLE : STD_LOGIC; 
  signal ResetCalc_GTS_OR_T : STD_LOGIC; 
  signal ResetCalc_O : STD_LOGIC; 
  signal SCLK_INBUF : STD_LOGIC; 
  signal INDSTATE_0_ENABLE : STD_LOGIC; 
  signal INDSTATE_0_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_0_O : STD_LOGIC; 
  signal OKforReset_ENABLE : STD_LOGIC; 
  signal OKforReset_GTS_OR_T : STD_LOGIC; 
  signal OKforReset_O : STD_LOGIC; 
  signal INDSTATE_1_ENABLE : STD_LOGIC; 
  signal INDSTATE_1_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_1_O : STD_LOGIC; 
  signal INDSTATE_2_ENABLE : STD_LOGIC; 
  signal INDSTATE_2_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_2_O : STD_LOGIC; 
  signal INDSTATE_3_ENABLE : STD_LOGIC; 
  signal INDSTATE_3_GTS_OR_T : STD_LOGIC; 
  signal INDSTATE_3_O : STD_LOGIC; 
  signal RESET_ENABLE : STD_LOGIC; 
  signal RESET_GTS_OR_T : STD_LOGIC; 
  signal RESET_O : STD_LOGIC; 
  signal START_INBUF : STD_LOGIC; 
  signal SCLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal ResetCalc_OBUF_F : STD_LOGIC; 
  signal ResetCalc_OBUF_DYMUX : STD_LOGIC; 
  signal ResetCalc_OBUF_G : STD_LOGIC; 
  signal ResetCalc_OBUF_SRFFMUX : STD_LOGIC; 
  signal ResetCalc_OBUF_CLKINV : STD_LOGIC; 
  signal ResetIndy_OBUF_DXMUX : STD_LOGIC; 
  signal ResetIndy_OBUF_F : STD_LOGIC; 
  signal ResetIndy_OBUF_G : STD_LOGIC; 
  signal ResetIndy_OBUF_SRFFMUX : STD_LOGIC; 
  signal ResetIndy_OBUF_CLKINV : STD_LOGIC; 
  signal OKforCalc_OBUF_DYMUX : STD_LOGIC; 
  signal OKforCalc_OBUF_G : STD_LOGIC; 
  signal OKforCalc_OBUF_SRFFMUX : STD_LOGIC; 
  signal OKforCalc_OBUF_CLKINV : STD_LOGIC; 
  signal RESET_OBUF_DXMUX : STD_LOGIC; 
  signal RESET_OBUF_F : STD_LOGIC; 
  signal RESET_OBUF_DYMUX : STD_LOGIC; 
  signal RESET_OBUF_G : STD_LOGIC; 
  signal RESET_OBUF_SRFFMUX : STD_LOGIC; 
  signal RESET_OBUF_CLKINV : STD_LOGIC; 
  signal OKforReset_OBUF_DXMUX : STD_LOGIC; 
  signal OKforReset_OBUF_F : STD_LOGIC; 
  signal OKforReset_OBUF_G : STD_LOGIC; 
  signal OKforReset_OBUF_SRFFMUX : STD_LOGIC; 
  signal OKforReset_OBUF_CLKINV : STD_LOGIC; 
  signal A_0_F : STD_LOGIC; 
  signal A_0_DYMUX : STD_LOGIC; 
  signal A_0_G : STD_LOGIC; 
  signal A_0_SRFFMUX : STD_LOGIC; 
  signal A_0_CLKINV : STD_LOGIC; 
  signal state_FFd10_DXMUX : STD_LOGIC; 
  signal state_FFd10_F : STD_LOGIC; 
  signal state_FFd10_BXINVNOT : STD_LOGIC; 
  signal state_FFd10_DYMUX : STD_LOGIC; 
  signal state_FFd10_G : STD_LOGIC; 
  signal state_FFd10_SRFFMUX : STD_LOGIC; 
  signal state_FFd10_SRINVNOT : STD_LOGIC; 
  signal state_FFd10_CLKINV : STD_LOGIC; 
  signal Q_n0012_1_F : STD_LOGIC; 
  signal state_FFd2_DXMUX : STD_LOGIC; 
  signal state_FFd2_DYMUX : STD_LOGIC; 
  signal state_FFd2_SRFFMUX : STD_LOGIC; 
  signal state_FFd2_SRINVNOT : STD_LOGIC; 
  signal state_FFd2_CLKINV : STD_LOGIC; 
  signal state_FFd4_DXMUX : STD_LOGIC; 
  signal state_FFd4_F : STD_LOGIC; 
  signal state_FFd4_DYMUX : STD_LOGIC; 
  signal state_FFd4_SRFFMUX : STD_LOGIC; 
  signal state_FFd4_SRINVNOT : STD_LOGIC; 
  signal state_FFd4_CLKINV : STD_LOGIC; 
  signal state_FFd6_DXMUX : STD_LOGIC; 
  signal state_FFd6_DYMUX : STD_LOGIC; 
  signal state_FFd6_SRFFMUX : STD_LOGIC; 
  signal state_FFd6_SRINVNOT : STD_LOGIC; 
  signal state_FFd6_CLKINV : STD_LOGIC; 
  signal state_FFd7_DXMUX : STD_LOGIC; 
  signal state_FFd7_F : STD_LOGIC; 
  signal state_FFd7_DYMUX : STD_LOGIC; 
  signal state_FFd7_G : STD_LOGIC; 
  signal state_FFd7_SRFFMUX : STD_LOGIC; 
  signal state_FFd7_SRINVNOT : STD_LOGIC; 
  signal state_FFd7_CLKINV : STD_LOGIC; 
  signal CHOICE326_F : STD_LOGIC; 
  signal CHOICE326_G : STD_LOGIC; 
  signal CHOICE316_F : STD_LOGIC; 
  signal state_FFd7_FFX_RST : STD_LOGIC; 
  signal state_FFd10_FFY_RST : STD_LOGIC; 
  signal state_FFd10_FFX_SET : STD_LOGIC; 
  signal state_FFd2_FFY_RST : STD_LOGIC; 
  signal state_FFd2_FFX_RST : STD_LOGIC; 
  signal INDSTATE_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_0 : STD_LOGIC; 
  signal INDSTATE_0_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal INDSTATE_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal INDSTATE_1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_1 : STD_LOGIC; 
  signal INDSTATE_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal INDSTATE_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal INDSTATE_2_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_2 : STD_LOGIC; 
  signal INDSTATE_2_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal INDSTATE_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal INDSTATE_3_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal INDSTATE_3 : STD_LOGIC; 
  signal INDSTATE_3_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal INDSTATE_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal state_FFd4_FFY_RST : STD_LOGIC; 
  signal state_FFd4_FFX_RST : STD_LOGIC; 
  signal state_FFd6_FFY_RST : STD_LOGIC; 
  signal state_FFd6_FFX_RST : STD_LOGIC; 
  signal state_FFd7_FFY_RST : STD_LOGIC; 
  signal A_1_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal RD_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal SDATA_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal Q_n0012 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  TESTMODE_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => TESTMODE,
      O => TESTMODE_INBUF
    );
  A_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_0_O,
      CTL => A_0_ENABLE,
      O => A(0)
    );
  A_0_ENABLEINV : X_INV
    port map (
      I => A_0_GTS_OR_T,
      O => A_0_ENABLE
    );
  A_0_GTS_OR_T_1 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => A_0_GTS_OR_T
    );
  A_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_1_O,
      CTL => A_1_ENABLE,
      O => A(1)
    );
  A_1_ENABLEINV : X_INV
    port map (
      I => A_1_GTS_OR_T,
      O => A_1_ENABLE
    );
  A_1_GTS_OR_T_2 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => A_1_GTS_OR_T
    );
  ResetIndy_OBUF_3 : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetIndy_O,
      CTL => ResetIndy_ENABLE,
      O => ResetIndy
    );
  ResetIndy_ENABLEINV : X_INV
    port map (
      I => ResetIndy_GTS_OR_T,
      O => ResetIndy_ENABLE
    );
  ResetIndy_GTS_OR_T_4 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => ResetIndy_GTS_OR_T
    );
  RD_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RD_O,
      CTL => RD_ENABLE,
      O => RD
    );
  RD_ENABLEINV : X_INV
    port map (
      I => RD_GTS_OR_T,
      O => RD_ENABLE
    );
  RD_GTS_OR_T_5 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => RD_GTS_OR_T
    );
  WR_OBUF_6 : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => WR_O,
      CTL => WR_ENABLE,
      O => WR
    );
  WR_ENABLEINV : X_INV
    port map (
      I => WR_GTS_OR_T,
      O => WR_ENABLE
    );
  WR_GTS_OR_T_7 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => WR_GTS_OR_T
    );
  D_0_IBUF_8 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(0),
      O => D_0_INBUF
    );
  D_1_IBUF_9 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(1),
      O => D_1_INBUF
    );
  D_2_IBUF_10 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(2),
      O => D_2_INBUF
    );
  D_3_IBUF_11 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(3),
      O => D_3_INBUF
    );
  D_4_IBUF_12 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(4),
      O => D_4_INBUF
    );
  SDATA_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SDATA_O,
      CTL => SDATA_ENABLE,
      O => SDATA
    );
  SDATA_ENABLEINV : X_INV
    port map (
      I => SDATA_GTS_OR_T,
      O => SDATA_ENABLE
    );
  SDATA_GTS_OR_T_13 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => SDATA_GTS_OR_T
    );
  OKforCalc_OBUF_14 : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforCalc_O,
      CTL => OKforCalc_ENABLE,
      O => OKforCalc
    );
  OKforCalc_ENABLEINV : X_INV
    port map (
      I => OKforCalc_GTS_OR_T,
      O => OKforCalc_ENABLE
    );
  OKforCalc_GTS_OR_T_15 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => OKforCalc_GTS_OR_T
    );
  D_5_IBUF_16 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(5),
      O => D_5_INBUF
    );
  D_6_IBUF_17 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(6),
      O => D_6_INBUF
    );
  D_7_IBUF_18 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(7),
      O => D_7_INBUF
    );
  ResetCalc_OBUF_19 : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetCalc_O,
      CTL => ResetCalc_ENABLE,
      O => ResetCalc
    );
  ResetCalc_ENABLEINV : X_INV
    port map (
      I => ResetCalc_GTS_OR_T,
      O => ResetCalc_ENABLE
    );
  ResetCalc_GTS_OR_T_20 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => ResetCalc_GTS_OR_T
    );
  SCLK_BUFGP_IBUFG_21 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK,
      O => SCLK_INBUF
    );
  INDSTATE_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_0_O,
      CTL => INDSTATE_0_ENABLE,
      O => INDSTATE(0)
    );
  INDSTATE_0_ENABLEINV : X_INV
    port map (
      I => INDSTATE_0_GTS_OR_T,
      O => INDSTATE_0_ENABLE
    );
  INDSTATE_0_GTS_OR_T_22 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_0_GTS_OR_T
    );
  OKforReset_OBUF_23 : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforReset_O,
      CTL => OKforReset_ENABLE,
      O => OKforReset
    );
  OKforReset_ENABLEINV : X_INV
    port map (
      I => OKforReset_GTS_OR_T,
      O => OKforReset_ENABLE
    );
  OKforReset_GTS_OR_T_24 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => OKforReset_GTS_OR_T
    );
  INDSTATE_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_1_O,
      CTL => INDSTATE_1_ENABLE,
      O => INDSTATE(1)
    );
  INDSTATE_1_ENABLEINV : X_INV
    port map (
      I => INDSTATE_1_GTS_OR_T,
      O => INDSTATE_1_ENABLE
    );
  INDSTATE_1_GTS_OR_T_25 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_1_GTS_OR_T
    );
  INDSTATE_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_2_O,
      CTL => INDSTATE_2_ENABLE,
      O => INDSTATE(2)
    );
  INDSTATE_2_ENABLEINV : X_INV
    port map (
      I => INDSTATE_2_GTS_OR_T,
      O => INDSTATE_2_ENABLE
    );
  INDSTATE_2_GTS_OR_T_26 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_2_GTS_OR_T
    );
  INDSTATE_3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_3_O,
      CTL => INDSTATE_3_ENABLE,
      O => INDSTATE(3)
    );
  INDSTATE_3_ENABLEINV : X_INV
    port map (
      I => INDSTATE_3_GTS_OR_T,
      O => INDSTATE_3_ENABLE
    );
  INDSTATE_3_GTS_OR_T_27 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_3_GTS_OR_T
    );
  RESET_OBUF_28 : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => RESET_O,
      CTL => RESET_ENABLE,
      O => RESET
    );
  RESET_ENABLEINV : X_INV
    port map (
      I => RESET_GTS_OR_T,
      O => RESET_ENABLE
    );
  RESET_GTS_OR_T_29 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => RESET_GTS_OR_T
    );
  START_IBUF_30 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => START,
      O => START_INBUF
    );
  SCLK_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => SCLK_BUFGP_IBUFG,
      I1 => GND,
      S => SCLK_BUFGP_BUFG_S_INVNOT,
      O => SCLK_BUFGP,
      GSR => GSR
    );
  SCLK_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1_0,
      O => SCLK_BUFGP_BUFG_S_INVNOT
    );
  ResetCalc_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetCalc_OBUF_F,
      O => N3067
    );
  ResetCalc_OBUF_DYMUX_31 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Q_n001311_O,
      O => ResetCalc_OBUF_DYMUX
    );
  ResetCalc_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ResetCalc_OBUF_G,
      O => Q_n001311_O
    );