fsm_map.vhd

VHDL source code for test machine.

      I => Indic_Q_10_DXMUX,
      CE => VCC,
      CLK => Indic_Q_10_CLKINV,
      SET => GND,
      RST => Indic_Q_10_FFX_RST,
      O => Indic_Q(10)
    );
  Indic_Q_10_FFX_RSTOR : X_OR2
    port map (
      I0 => Indic_Q_10_SRFFMUX,
      I1 => GSR,
      O => Indic_Q_10_FFX_RST
    );
  Indic_Q_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Indic_Q_18_DYMUX,
      CE => VCC,
      CLK => Indic_Q_18_CLKINV,
      SET => GND,
      RST => Indic_Q_18_FFY_RST,
      O => Indic_Q(19)
    );
  Indic_Q_18_FFY_RSTOR : X_OR2
    port map (
      I0 => Indic_Q_18_SRFFMUX,
      I1 => GSR,
      O => Indic_Q_18_FFY_RST
    );
  Indic_Q_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Indic_Q_18_DXMUX,
      CE => VCC,
      CLK => Indic_Q_18_CLKINV,
      SET => GND,
      RST => Indic_Q_18_FFX_RST,
      O => Indic_Q(18)
    );
  Indic_Q_18_FFX_RSTOR : X_OR2
    port map (
      I0 => Indic_Q_18_SRFFMUX,
      I1 => GSR,
      O => Indic_Q_18_FFX_RST
    );
  A_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => A_1_O,
      CTL => A_1_ENABLE,
      O => A(1)
    );
  A_1_ENABLEINV : X_INV
    port map (
      I => A_1_GTS_OR_T,
      O => A_1_ENABLE
    );
  A_1_GTS_OR_T_167 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => A_1_GTS_OR_T
    );
  Indy_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => Indy_O,
      CTL => Indy_ENABLE,
      O => Indy
    );
  Indy_ENABLEINV : X_INV
    port map (
      I => Indy_GTS_OR_T,
      O => Indy_ENABLE
    );
  Indy_GTS_OR_T_168 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => Indy_GTS_OR_T
    );
  D_0_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_0_O,
      CTL => D_0_ENABLE,
      O => D(0)
    );
  D_0_ENABLEINV : X_INV
    port map (
      I => D_0_GTS_OR_T,
      O => D_0_ENABLE
    );
  D_0_GTS_OR_T_169 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_0_T,
      O => D_0_GTS_OR_T
    );
  D_0_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(0),
      O => D_0_INBUF
    );
  D_1_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_1_O,
      CTL => D_1_ENABLE,
      O => D(1)
    );
  D_1_ENABLEINV : X_INV
    port map (
      I => D_1_GTS_OR_T,
      O => D_1_ENABLE
    );
  D_1_GTS_OR_T_170 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_1_T,
      O => D_1_GTS_OR_T
    );
  D_1_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(1),
      O => D_1_INBUF
    );
  D_2_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_2_O,
      CTL => D_2_ENABLE,
      O => D(2)
    );
  D_2_ENABLEINV : X_INV
    port map (
      I => D_2_GTS_OR_T,
      O => D_2_ENABLE
    );
  D_2_GTS_OR_T_171 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_2_T,
      O => D_2_GTS_OR_T
    );
  D_2_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(2),
      O => D_2_INBUF
    );
  D_3_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_3_O,
      CTL => D_3_ENABLE,
      O => D(3)
    );
  D_3_ENABLEINV : X_INV
    port map (
      I => D_3_GTS_OR_T,
      O => D_3_ENABLE
    );
  D_3_GTS_OR_T_172 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_3_T,
      O => D_3_GTS_OR_T
    );
  D_3_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(3),
      O => D_3_INBUF
    );
  D_4_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_4_O,
      CTL => D_4_ENABLE,
      O => D(4)
    );
  D_4_ENABLEINV : X_INV
    port map (
      I => D_4_GTS_OR_T,
      O => D_4_ENABLE
    );
  D_4_GTS_OR_T_173 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_4_T,
      O => D_4_GTS_OR_T
    );
  D_4_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(4),
      O => D_4_INBUF
    );
  OKforCalc_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforCalc_O,
      CTL => OKforCalc_ENABLE,
      O => OKforCalc
    );
  OKforCalc_ENABLEINV : X_INV
    port map (
      I => OKforCalc_GTS_OR_T,
      O => OKforCalc_ENABLE
    );
  OKforCalc_GTS_OR_T_174 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => OKforCalc_GTS_OR_T
    );
  SDATA_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SDATA_O,
      CTL => SDATA_ENABLE,
      O => SDATA
    );
  SDATA_ENABLEINV : X_INV
    port map (
      I => SDATA_GTS_OR_T,
      O => SDATA_ENABLE
    );
  SDATA_GTS_OR_T_175 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => SDATA_GTS_OR_T
    );
  D_5_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_5_O,
      CTL => D_5_ENABLE,
      O => D(5)
    );
  D_5_ENABLEINV : X_INV
    port map (
      I => D_5_GTS_OR_T,
      O => D_5_ENABLE
    );
  D_5_GTS_OR_T_176 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_5_T,
      O => D_5_GTS_OR_T
    );
  D_5_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(5),
      O => D_5_INBUF
    );
  D_6_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_6_O,
      CTL => D_6_ENABLE,
      O => D(6)
    );
  D_6_ENABLEINV : X_INV
    port map (
      I => D_6_GTS_OR_T,
      O => D_6_ENABLE
    );
  D_6_GTS_OR_T_177 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_6_T,
      O => D_6_GTS_OR_T
    );
  D_6_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(6),
      O => D_6_INBUF
    );
  Indic_Q_LPM_COUNTER_1_n0000_0_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Indic_Q(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Indic_Q_0_F
    );
  D_7_IOBUF_OBUFT : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D_7_O,
      CTL => D_7_ENABLE,
      O => D(7)
    );
  D_7_ENABLEINV : X_INV
    port map (
      I => D_7_GTS_OR_T,
      O => D_7_ENABLE
    );
  D_7_GTS_OR_T_178 : X_OR2
    port map (
      I0 => GTS,
      I1 => D_7_T,
      O => D_7_GTS_OR_T
    );
  D_7_IOBUF_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => D(7),
      O => D_7_INBUF
    );
  SCLK_BUFGP_IBUFG_179 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SCLK,
      O => SCLK_INBUF
    );
  INDSTATE_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_0_O,
      CTL => INDSTATE_0_ENABLE,
      O => INDSTATE(0)
    );
  INDSTATE_0_ENABLEINV : X_INV
    port map (
      I => INDSTATE_0_GTS_OR_T,
      O => INDSTATE_0_ENABLE
    );
  INDSTATE_0_GTS_OR_T_180 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_0_GTS_OR_T
    );
  INDSTATE_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_1_O,
      CTL => INDSTATE_1_ENABLE,
      O => INDSTATE(1)
    );
  INDSTATE_1_ENABLEINV : X_INV
    port map (
      I => INDSTATE_1_GTS_OR_T,
      O => INDSTATE_1_ENABLE
    );
  INDSTATE_1_GTS_OR_T_181 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_1_GTS_OR_T
    );
  INDSTATE_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_2_O,
      CTL => INDSTATE_2_ENABLE,
      O => INDSTATE(2)
    );
  INDSTATE_2_ENABLEINV : X_INV
    port map (
      I => INDSTATE_2_GTS_OR_T,
      O => INDSTATE_2_ENABLE
    );
  INDSTATE_2_GTS_OR_T_182 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_2_GTS_OR_T
    );
  INDSTATE_3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => INDSTATE_3_O,
      CTL => INDSTATE_3_ENABLE,
      O => INDSTATE(3)
    );
  INDSTATE_3_ENABLEINV : X_INV
    port map (
      I => INDSTATE_3_GTS_OR_T,
      O => INDSTATE_3_ENABLE
    );
  INDSTATE_3_GTS_OR_T_183 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => INDSTATE_3_GTS_OR_T
    );
  nIndy_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => nIndy_O,
      CTL => nIndy_ENABLE,
      O => nIndy
    );
  nIndy_ENABLEINV : X_INV
    port map (
      I => nIndy_GTS_OR_T,
      O => nIndy_ENABLE
    );
  nIndy_GTS_OR_T_184 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => nIndy_GTS_OR_T
    );
  START_IBUF_185 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => START,
      O => START_INBUF
    );
  OKforReset_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => OKforReset_O,
      CTL => OKforReset_ENABLE,
      O => OKforReset
    );
  OKforReset_ENABLEINV : X_INV
    port map (
      I => OKforReset_GTS_OR_T,
      O => OKforReset_ENABLE
    );
  OKforReset_GTS_OR_T_186 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => OKforReset_GTS_OR_T
    );
  SCLK_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => SCLK_BUFGP_IBUFG,
      I1 => GND,