project.cmd_log

VHDL source code for test machine.

xst -intstyle ise -ifn __projnav/project.xst -ofn project.syr
ngdbuild -intstyle ise -dd d:\csht\final15.06.07\project\importantversion/_ngo -i  -p xc2v40-fg256-5 project.ngc project.ngd
map -intstyle ise -p xc2v40-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o project_map.ncd project.ngd project.pcf
par -w -intstyle ise -ol std -t 1 project_map.ncd project.ncd project.pcf
trce -intstyle ise -e 3 -l 3 -xml project project.ncd -o project.twr project.pcf
netgen -intstyle ise -s 5   -pcf project.pcf -ngm project.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim project.ncd project_timesim.vhd