indicator.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity indicator is
	port ( RESET  : in std_logic;
			 CLK_IN : in std_logic;
			 Indy	  : out std_logic;
			 nIndy  : out std_logic
			);
end indicator;

architecture Behavioral of indicator is

	signal Q : std_logic_vector(22 downto 0);

begin

process ( RESET, CLK_IN )
begin
	if RESET = '1'	then Q <=( others=> '0');
	elsif CLK_IN'event AND CLK_IN = '1' then Q <=Q+1;
	end if;

	Indy <=Q(22);
	nIndy <=not Q(22);
end process;

end Behavioral;