or1_ent.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity or1_ent is

	port(D_IN : in std_logic_vector(1 downto 0);
		  D_OUT : out std_logic 
		  );
end or1_ent;

architecture Behavioral of or1_ent is

begin

	 	 D_OUT <= D_IN(0) or D_IN(1);

end Behavioral;