transcript

VHDL source code for test machine.

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do test2.tdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity fsm
# -- Compiling architecture structure of fsm
# -- Loading entity x_zero
# -- Loading entity x_one
# -- Loading entity x_buf_pp
# -- Loading entity x_mux2
# -- Loading entity x_inv
# -- Loading entity x_xor2
# -- Loading entity x_and2
# -- Loading entity x_ff
# -- Loading entity x_or2
# -- Loading entity x_tri_pp
# -- Loading entity x_lut4
# -- Loading entity x_bufgmux
# -- Loading entity x_sff
# -- Loading package vital_timing
# -- Loading entity x_roc
# -- Loading entity x_toc
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test2
# -- Compiling architecture testbench_arch of test2
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package vpackage
# -- Loading entity fsm
# -- Compiling configuration fsm_cfg
# -- Loading entity test2
# -- Loading architecture testbench_arch of test2
# vsim -lib work -sdfmax /UUT=fsm_timesim.sdf -t 1ps test2 
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../vital2000.vital_timing(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vcomponents
# Loading C:\Modeltech_xe_starter\win32xoem/../vital2000.vital_primitives(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vpackage(body)
# Loading work.test2(testbench_arch)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body)
# Loading work.fsm(structure)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_buf_pp(x_buf_pp_v)
# Loading fsm_timesim.sdf
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_xor2(x_xor2_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_and2(x_and2_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_or2(x_or2_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_tri_pp(x_tri_pp_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_bufgmux(x_bufgmux_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_sff(x_sff_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.vital_primitives(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v)
# ** Warning: Design size of 5724 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Region: /test2  File: test2.timesim_vhw
# .wave
# .structure
# .signals
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 910 ns  Iteration: 0  Process: /test2/line__86 File: test2.timesim_vhw
# Break at test2.timesim_vhw line 304
# Simulation Breakpoint: Break at test2.timesim_vhw line 304
# MACRO ./test2.tdo PAUSED at line 14