reg8.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reg8 is

	port (D		: in std_logic_vector (7 downto 0);
	      Q		: out std_logic_vector (7 downto 0);
		 	CLK	: in std_logic;
			CLR	: in std_logic
		 );
end reg8;

architecture Behavioral of reg8 is

begin

	  process(D, CLK, CLR)
    		begin

				if CLR = '0' then							 --CLR e aktiven po 0
            	Q <= "00000000";						 --nulirane na registura,
				elsif (CLK='1' and CLK'event) then	 -- pri CLR=1 i CLK=1
					Q <= D;									 --tova,koeto e na vhoda, se poqvqva i na izhoda
				end if;
    	end process;

end Behavioral;