project.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity project is
		   port ( 	A 		  : in std_logic_vector (1 downto 0);
						SDATA	  : in std_logic;
						SCLK 	  : in std_logic;
 						RESET   : in std_logic ;
						WR 	  : in std_logic;
						RD		  : in std_logic;
						D		  : out std_logic_vector (7 downto 0);
						REG_OUT : inout std_logic_vector (7 downto 0);
						IRQ	  : out std_logic	
			   );
end project;

architecture Structural of project is


component sreg8
    	port (DIN	: in std_logic;
	      	Q		: out std_logic_vector (8 downto 0);
		 		CLK	: in std_logic;
		 		CLR	: in std_logic
		 );
end component;
----------------------------------------------------
component reg8
		port (D		: in std_logic_vector (7 downto 0);
	      	Q		: out std_logic_vector (7 downto 0);
		 		CLK	: in std_logic;
				CLR	: in std_logic
		 );
end component;	
-------------------------------------------------------
component buf8
		port	(OE	: in std_logic;
			  	 A	: in std_logic_vector(7 downto 0);
			  	 Y	: out std_logic_vector(7 downto 0)
			);
end component;
--------------------------------------------------------
component dec2to4
		port  (A	: in std_logic_vector(1 downto 0);
			    Y	: out std_logic_vector(3 downto 0) 
			);
end component;
--------------------------------------------------
component or1_ent
		port(D_IN  : in std_logic_vector(1 downto 0);
			  D_OUT : out std_logic 
			);
end component;
---------------------------------------------------
component or2_ent
		port(D_IN  : in std_logic_vector(1 downto 0);
			  D_OUT : out std_logic 
			);
end component;
---------------------------------------------------
component and_ent
		port(D_IN : in std_logic_vector(1 downto 0);
			  D_OUT : out std_logic 
			);
end component;
----------------------------------------------------

signal SREG_OUT								: std_logic_vector (7 downto 0);
signal DEC_OUT				 								: std_logic_vector (3 downto 0);
signal OR1_OUT,OR2_OUT,AND_OUT,SREG_Q8      	   : std_logic;

---------------------BODY -------------------------------------------------------------------

begin

  sreg: sreg8  port map (DIN => SDATA,
								 Q(7 downto 0) => SREG_OUT,
								 Q(8) => SREG_Q8,
								 CLK => SCLK,
								 CLR => AND_OUT);

  reg : reg8   port map (D => SREG_OUT, 
  								 Q => REG_OUT, 
								 CLK => SREG_Q8,
								 CLR => AND_OUT);

  buf:buf8     port map (A  => REG_OUT, 
  								 Y  => D,
								 OE => OR2_OUT);

  dec:dec2to4  port map (A => A,
  								 Y => DEC_OUT);

  or1:or1_ent  port map (D_IN(0) => DEC_OUT(0),
  								 D_IN(1) => WR,
								 D_OUT => OR1_OUT);

  or2:or2_ent  port map (D_IN(0) => DEC_OUT(1),
  								 D_IN(1) => RD,
								 D_OUT => OR2_OUT);

  and1:and_ent port map (D_IN(0) => RESET,
  								 D_IN(1) => OR1_OUT,
								 D_OUT => AND_OUT);


  IRQ  <= SREG_Q8;

end Structural;