project.syr

VHDL source code for test machine.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 10
 1-bit register                    : 9
 8-bit register                    : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <project> ...
Loading device for application Xst from file '2v40.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block project, actual ratio is 3.
FlipFlop reg_Q_0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop reg_Q_7 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : project.ngr
Top Level Output File Name         : project
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 24

Macro Statistics :
# Registers                        : 10
#      1-bit register              : 9
#      8-bit register              : 1
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 2
#      LUT3                        : 1
#      LUT4                        : 1
# FlipFlops/Latches                : 25
#      FDC                         : 25
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 23
#      IBUF                        : 6
#      OBUF                        : 9
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      14  out of    256     5%  
 Number of Slice Flip Flops:            25  out of    512     4%  
 Number of 4 input LUTs:                 2  out of    512     0%  
 Number of bonded IOBs:                 23  out of     88    26%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sreg_REG_8:Q                       | NONE                   | 16    |
SCLK                               | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 1.446ns (Maximum Frequency: 691.563MHz)
   Minimum input arrival time before clock: 1.490ns
   Maximum output required time after clock: 5.270ns
   Maximum combinational path delay: 6.276ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'SCLK'
Delay:               1.446ns (Levels of Logic = 0)
  Source:            sreg_REG_0 (FF)
  Destination:       sreg_REG_1 (FF)
  Source Clock:      SCLK rising
  Destination Clock: SCLK rising

  Data Path: sreg_REG_0 to sreg_REG_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.494   0.630  sreg_REG_0 (sreg_REG_0)
     FDC:D                     0.322          sreg_REG_1
    ----------------------------------------
    Total                      1.446ns (0.816ns logic, 0.630ns route)
                                       (56.4% logic, 43.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'SCLK'
Offset:              1.490ns (Levels of Logic = 1)
  Source:            SDATA (PAD)
  Destination:       sreg_REG_0 (FF)
  Destination Clock: SCLK rising

  Data Path: SDATA to sreg_REG_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.718   0.450  SDATA_IBUF (SDATA_IBUF)
     FDC:D                     0.322          sreg_REG_0
    ----------------------------------------
    Total                      1.490ns (1.040ns logic, 0.450ns route)
                                       (69.8% logic, 30.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'sreg_REG_8:Q'
Offset:              4.840ns (Levels of Logic = 1)
  Source:            reg_Q_0_1 (FF)
  Destination:       REG_OUT<0> (PAD)
  Source Clock:      sreg_REG_8:Q rising

  Data Path: reg_Q_0_1 to REG_OUT<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.494   0.450  reg_Q_0_1 (reg_Q_0_1)
     OBUF:I->O                 3.896          REG_OUT_0_OBUF (REG_OUT<0>)
    ----------------------------------------
    Total                      4.840ns (4.390ns logic, 0.450ns route)
                                       (90.7% logic, 9.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'SCLK'
Offset:              5.270ns (Levels of Logic = 1)
  Source:            sreg_REG_8 (FF)
  Destination:       IRQ (PAD)
  Source Clock:      SCLK rising

  Data Path: sreg_REG_8 to IRQ
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             17   0.494   0.880  sreg_REG_8 (sreg_REG_8)
     OBUF:I->O                 3.896          IRQ_OBUF (IRQ)
    ----------------------------------------
    Total                      5.270ns (4.390ns logic, 0.880ns route)
                                       (83.3% logic, 16.7% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               6.276ns (Levels of Logic = 3)
  Source:            A<1> (PAD)
  Destination:       D<7> (PAD)

  Data Path: A<1> to D<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.718   0.610  A_1_IBUF (A_1_IBUF)
     LUT3:I0->O            8   0.382   0.730  or2_D_OUT1 (OR2_OUT)
     OBUFT:T->O                3.836          D_1_OBUFT (D<1>)
    ----------------------------------------
    Total                      6.276ns (4.936ns logic, 1.340ns route)
                                       (78.6% logic, 21.4% route)

=========================================================================
CPU : 12.22 / 13.97 s | Elapsed : 12.00 / 14.00 s
 
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Total memory usage is 63116 kilobytes