project.syr

VHDL source code for test machine.

Release 6.3.03i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: project.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : project.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : project
Output Format                      : NGC
Target Device                      : xc2v40-5-fg256

---- Source Options
Top Module Name                    : project
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : project.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/sreg8.vhd in Library work.
Architecture behavioral of Entity sreg8 is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/reg8.vhd in Library work.
Architecture behavioral of Entity reg8 is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/buf8.vhd in Library work.
Architecture behavioral of Entity buf8 is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/dec2to4.vhd in Library work.
Architecture behavioral of Entity dec2to4 is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/or1_ent.vhd in Library work.
Architecture behavioral of Entity or1_ent is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/or2_ent.vhd in Library work.
Architecture behavioral of Entity or2_ent is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/and_ent.vhd in Library work.
Architecture behavioral of Entity and_ent is up to date.
Compiling vhdl file D:/CShT/Final15.06.07/Project/ImportantVersion/project.vhd in Library work.
Architecture structural of Entity project is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <project> (Architecture <structural>).
Entity <project> analyzed. Unit <project> generated.

Analyzing Entity <sreg8> (Architecture <behavioral>).
WARNING:Xst:819 - D:/CShT/Final15.06.07/Project/ImportantVersion/sreg8.vhd line 26: The following signals are missing in the process sensitivity list:
   CLR, REG.
Entity <sreg8> analyzed. Unit <sreg8> generated.

Analyzing Entity <reg8> (Architecture <behavioral>).
Entity <reg8> analyzed. Unit <reg8> generated.

Analyzing Entity <buf8> (Architecture <behavioral>).
Entity <buf8> analyzed. Unit <buf8> generated.

Analyzing Entity <dec2to4> (Architecture <behavioral>).
Entity <dec2to4> analyzed. Unit <dec2to4> generated.

Analyzing Entity <or1_ent> (Architecture <behavioral>).
Entity <or1_ent> analyzed. Unit <or1_ent> generated.

Analyzing Entity <or2_ent> (Architecture <behavioral>).
Entity <or2_ent> analyzed. Unit <or2_ent> generated.

Analyzing Entity <and_ent> (Architecture <behavioral>).
Entity <and_ent> analyzed. Unit <and_ent> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <and_ent>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/and_ent.vhd.
Unit <and_ent> synthesized.


Synthesizing Unit <or2_ent>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/or2_ent.vhd.
Unit <or2_ent> synthesized.


Synthesizing Unit <or1_ent>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/or1_ent.vhd.
Unit <or1_ent> synthesized.


Synthesizing Unit <dec2to4>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/dec2to4.vhd.
    Found 1-of-4 decoder for signal <Y>.
    Summary:
	inferred   1 Decoder(s).
Unit <dec2to4> synthesized.


Synthesizing Unit <buf8>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/buf8.vhd.
    Found 8-bit tristate buffer for signal <Y>.
    Summary:
	inferred   8 Tristate(s).
Unit <buf8> synthesized.


Synthesizing Unit <reg8>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/reg8.vhd.
    Found 8-bit register for signal <Q>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <reg8> synthesized.


Synthesizing Unit <sreg8>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/sreg8.vhd.
    Found 9-bit register for signal <REG>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <sreg8> synthesized.


Synthesizing Unit <project>.
    Related source file is D:/CShT/Final15.06.07/Project/ImportantVersion/project.vhd.
WARNING:Xst:646 - Signal <DEC_OUT<3:2>> is assigned but never used.
Unit <project> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...