buf8.vhd

VHDL source code for test machine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity buf8 is

	port(  OE	: in std_logic;
			 A	: in std_logic_vector(7 downto 0);
			 Y	: out std_logic_vector(7 downto 0)
		  );

end buf8;

architecture Behavioral of buf8 is

begin
	  process (OE, A)
	  		begin
				if (OE = '0') then		   --OE-razreshavasht vhod; aktiven e po 0
					Y <= A;					   --izhodut kopira vhoda
				else							   --Ako OE=1
					Y <= (others => 'Z');	--Izhodut se namira vuv visokoimpedansno sustoqnie
				end if;
		end process;

end Behavioral;