test1.fdo

VHDL source code for test machine.

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 26 12:58:53 E. Europe Daylight Time 2007
##
vlib work
vcom -93 -explicit  testmachine.vhd
vcom -93 -explicit  sreg8.vhd
vcom -93 -explicit  reg8.vhd
vcom -93 -explicit  buf8.vhd
vcom -93 -explicit  dec2to4.vhd
vcom -93 -explicit  or1_ent.vhd
vcom -93 -explicit  or2_ent.vhd
vcom -93 -explicit  and_ent.vhd
vcom -93 -explicit  project.vhd
vcom -93 -explicit  indicator.vhd
vcom -93 -explicit  fsm.vhd
vcom -93 -explicit  test1.vhw
vsim -t 1ps   -lib work test1
do test1.udo
view wave
add wave *
view structure
view signals
run -all